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Changes to build with a 512-bit main data bus (with all other busses

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still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
This commit is contained in:
Jonathan Woodruff
2022-11-11 17:52:32 +00:00
parent 066289f8aa
commit ddf4afaf71
8 changed files with 41 additions and 29 deletions
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16
src_Testbench/SoC/Mem_Controller.bsv
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@@ -126,7 +126,7 @@ typedef TLog #(Word64s_per_Raw_Mem_Word) Bits_per_Word64_in_Raw_Me
// Type of index of a Word64 in a Raw_Mem_Word seen as a vector of Word64s
typedef Bit #(Bits_per_Word64_in_Raw_Mem_Word) Word64_in_Raw_Mem_Word;
typedef TDiv #(Bytes_per_Raw_Mem_Word, Bytes_per_Fabric_Data) Fabric_Data_per_Raw_Mem_Word;
typedef TDiv #(Bytes_per_Raw_Mem_Word, TDiv #(Wd_Data_Periph, 8)) Fabric_Data_per_Raw_Mem_Word;
// Index of bit that selects a fabric data word in an address
`ifdef FABRIC32
@@ -207,7 +207,7 @@ interface Mem_Controller_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
slave;
// To raw memory (outside the SoC)
@@ -245,8 +245,8 @@ typedef struct {Req_Op req_op;
Bit #(Wd_User) user;
// Write data info
Bit #(TDiv #(Wd_Data, 8)) wstrb;
Fabric_Data data;
Bit #(TDiv #(Wd_Data_Periph, 8)) wstrb;
Bit #(Wd_Data_Periph) data;
} Req
deriving (Bits, FShow);
@@ -487,7 +487,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// We need to select the fabric data word from the raw mem word that contains the target address.
// View the raw mem word as a vector of fabric data words (Wd_Data width words)
Vector #(Fabric_Data_per_Raw_Mem_Word, Bit #(Wd_Data)) raw_mem_word_V_fabric_data = unpack (rg_cached_raw_mem_word);
Vector #(Fabric_Data_per_Raw_Mem_Word, Bit #(Wd_Data_Periph)) raw_mem_word_V_fabric_data = unpack (rg_cached_raw_mem_word);
// Get the index into this vector of the fabric word containing the target address.
// For this index, use a generous size (here Bit #(16)), and let zeroExtend pad it automaticallly.
@@ -496,7 +496,7 @@ module mkMem_Controller (Mem_Controller_IFC);
n = (n >> lo_fabric_data);
// Select the fabric data word of interest
Bit #(Wd_Data) rdata = raw_mem_word_V_fabric_data [n];
Bit #(Wd_Data_Periph) rdata = raw_mem_word_V_fabric_data [n];
let rdr = AXI4_RFlit {rid: f_reqs.first.id,
rdata: rdata,
@@ -529,7 +529,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// Lane-adjust the new word64
Bit #(64) word64_new = zeroExtend (f_reqs.first.data);
Bit #(8) strobe = zeroExtend (f_reqs.first.wstrb);
if ((valueOf (Wd_Data) == 32) && (f_reqs.first.addr [2] == 1'b1)) begin
if ((valueOf (Wd_Data_Periph) == 32) && (f_reqs.first.addr [2] == 1'b1)) begin
// Upper 32b only
word64_new = { word64_new [31:0], 0 };
strobe = { strobe [3:0], 0 };
@@ -609,7 +609,7 @@ module mkMem_Controller (Mem_Controller_IFC);
rule rl_invalid_rd_address ( (rg_state == STATE_READY)
&& (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size))
&& (f_reqs.first.req_op == REQ_OP_RD));
Fabric_Data rdata = zeroExtend (f_reqs.first.addr);
Bit#(Wd_Data_Periph) rdata = zeroExtend (f_reqs.first.addr);
let rdr = AXI4_RFlit {rid: f_reqs.first.id,
rdata: rdata, // for debugging only
rresp: SLVERR,