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changed _Synth to _Sig following the new convention in BlueStuff

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This commit is contained in:
Franz Fuchs
2021-09-30 15:02:47 +01:00
parent b4fe3ee93c
commit df74a71d61
2 changed files with 14 additions and 14 deletions
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16
src_SSITH_P3/src_BSV/Giraffe_IFC.bsv
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@@ -118,10 +118,10 @@ instance Connectable#(DMI_IFC, DMI_Master_IFC);
endinstance
interface Core_IFC;
interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master0;
interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master1;
interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master2;
interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master3;
interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master0;
interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master1;
interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master2;
interface AXI4_Master_Sig#(`AXI4_PARAMS_Giraffe) master3;
(* always_ready, always_enabled *)
(* prefix = "", result = "unused0" *)
@@ -145,10 +145,10 @@ interface Core_IFC;
endinterface
interface Platform_IFC;
interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave0;
interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave1;
interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave2;
interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave3;
interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave0;
interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave1;
interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave2;
interface AXI4_Slave_Sig#(`AXI4_PARAMS_Giraffe) slave3;
(* always_ready, always_enabled *)
method Bit#(1) interrupt0;

12
src_SSITH_P3/src_BSV/P3_Core.bsv
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@@ -70,10 +70,10 @@ interface P3_Core_IFC;
// Core CPU interfaces
// CPU IMem to Fabric master interface
interface AXI4_Master_Synth#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) master0;
interface AXI4_Master_Synth#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) master1;
// External interrupt sources
@@ -293,16 +293,16 @@ module mkP3_Core (P3_Core_IFC);
// ================================================================
// INTERFACE
let master0_synth <- toAXI4_Master_Synth(corew.cpu_imem_master);
let master1_synth <- toAXI4_Master_Synth(corew.cpu_dmem_master);
let master0_sig <- toAXI4_Master_Sig(corew.cpu_imem_master);
let master1_sig <- toAXI4_Master_Sig(corew.cpu_dmem_master);
// ----------------------------------------------------------------
// Core CPU interfaces
// CPU IMem to Fabric master interface
interface AXI4_Master_Synth master0 = master0_synth;
interface AXI4_Master_Sig master0 = master0_sig;
// CPU DMem to Fabric master interface
interface AXI4_Master_Synth master1 = master1_synth;
interface AXI4_Master_Sig master1 = master1_sig;
// External interrupts
method Action interrupt_reqs (Bit #(N_External_Interrupt_Sources) reqs);