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Merge branch 'CHERI' into jdw57_schedule_experiments_III

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This commit is contained in:
Jonathan Woodruff
2022-02-14 16:01:47 +00:00
parent 886854faec 05df76073b
commit e118e7c0ee
5 changed files with 56 additions and 18 deletions
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1
src_Core/CPU/Core.bsv
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@@ -650,6 +650,7 @@ module mkCore#(CoreId coreId)(Core);
method stbEmpty = stb.isEmpty;
method stqEmpty = lsq.stqEmpty;
method lsqSetAtCommit = lsq.setAtCommit;
method lookupPAddr = lsq.lookupPAddr;
method pauseCommit = coreFix.pendingIncorrectSpec;
method tlbNoPendingReq = iTlb.noPendingReq && dTlb.noPendingReq;

14
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -60,6 +60,7 @@ import RenameDebugIF::*;
import CHERICap::*;
import CHERICC_Fat::*;
import ISA_Decls_CHERI::*;
import RegFile::*; // Just for the interface
`ifdef PERFORMANCE_MONITORING
import StatCounters::*;
`endif
@@ -106,6 +107,8 @@ interface CommitInput;
method Bool stqEmpty;
// notify LSQ that inst has reached commit
interface Vector#(SupSize, Put#(LdStQTag)) lsqSetAtCommit;
// method for getting translated addresses for tracing.
interface Vector#(SupSize, RegFile#(LdStQTag, Addr)) lookupPAddr;
// TLB has stopped processing now
method Bool tlbNoPendingReq;
// Pause committing, probably for buffered wrongSpec
@@ -213,7 +216,7 @@ typedef struct {
Data mtvec;
} TraceStateBundle deriving(Bits, FShow);
function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot, Dii_Id traceCnt, TraceStateBundle tsb, Data next_pc);
function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot, Dii_Id traceCnt, TraceStateBundle tsb, Data next_pc, Addr paddr);
Addr addr = 0;
Data data = 0;
Data wdata = 0;
@@ -230,6 +233,9 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot,
case (rot.ppc_vaddr_csrData) matches
tagged VAddr .vaddr: begin
addr = vaddr;
`ifdef PADDR_RVFI
addr = paddr;
`endif
case (rot.lsqTag) matches
tagged Ld .l: rmask = rot.traceBundle.memByteEn;
tagged St .s: begin
@@ -800,7 +806,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
});
`ifdef RVFI
Rvfi_Traces rvfis = replicate(tagged Invalid);
rvfis[0] = genRVFI(trap.x, traceCnt, getTSB(), getAddr(new_pc));
rvfis[0] = genRVFI(trap.x, traceCnt, getTSB(), getAddr(new_pc), inIfc.lookupPAddr[0].sub(trap.x.lsqTag));
rvfiQ.enq(rvfis);
traceCnt <= traceCnt + 1;
`endif
@@ -969,7 +975,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Rvfi_Traces rvfis = replicate(tagged Invalid);
x.ppc_vaddr_csrData = tagged PPC next_pc;
CapPipe cp = cast(next_pc);
rvfis[0] = genRVFI(x, traceCnt, getTSB(), getOffset(cp));
rvfis[0] = genRVFI(x, traceCnt, getTSB(), getOffset(cp), inIfc.lookupPAddr[0].sub(x.lsqTag));
rvfiQ.enq(rvfis);
traceCnt <= traceCnt + 1;
`endif
@@ -1147,7 +1153,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (verbose) $display("%t : [doCommitNormalInst - %d] ", $time(), i, fshow(inst_tag), " ; ", fshow(x));
`ifdef RVFI
CapPipe pipePc = cast(x.pc);
rvfis[i] = genRVFI(x, traceCnt + zeroExtend(whichTrace), getTSB(), getOffset(pipePc) + (is_16b_inst(x.orig_inst) ? 2:4));
rvfis[i] = genRVFI(x, traceCnt + zeroExtend(whichTrace), getTSB(), getOffset(pipePc) + (is_16b_inst(x.orig_inst) ? 2:4), inIfc.lookupPAddr[i].sub(x.lsqTag));
whichTrace = whichTrace + 1;
`endif

24
src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
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@@ -167,6 +167,30 @@
// ==== CORE SIZE ====
//
`ifdef CORE_MINI
// superscalar
`define sizeSup 2
// ROB
`define ROB_SIZE 32
// speculation
`define NUM_EPOCHS 4
`define NUM_SPEC_TAGS 4
// LSQ
`define LDQ_SIZE 8
`define STQ_SIZE 4
`define SB_SIZE 2
// reservation station sizes
`define RS_ALU_SIZE 8
`define RS_MEM_SIZE 4
`define RS_FPUMULDIV_SIZE 4
`endif
`ifdef CORE_TINY
// superscalar

20
src_Core/RISCY_OOO/procs/lib/GlobalSpecUpdate.bsv
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@@ -54,10 +54,8 @@ module mkGlobalSpecUpdate#(
);
// record correct spec tags
Vector#(correctSpecPortNum, RWire#(SpecTag)) correctSpecTag <- replicateM(mkRWire);
// make wrong spec conflict with correct spec
Vector#(correctSpecPortNum, PulseWire) spec_conflict <- replicateM(mkPulseWire);
// let the caller of conflictWrongSpec to be conflict with wrong spec
Vector#(conflictWrongSpecPortNum, PulseWire) wrongSpec_conflict <- replicateM(mkPulseWire);
// make wrong spec conflict with correct spec and conflictWrongSpec
PulseWire spec_conflict <- mkPulseWire;
// must be a single-element fifo to ensure all pushing rules cannot fire while we are waiting
// to kill.
SpecFifo#(2,IncorrectSpec,1,1) incorrectSpec_ff <- mkSpecFifoCF(True);
@@ -81,20 +79,14 @@ module mkGlobalSpecUpdate#(
incorrectSpec_ff.specUpdate.incorrectSpeculation(x.kill_all, x.spec_tag);
ifc.incorrectSpeculation(x.kill_all, x.spec_tag);
rob.incorrectSpeculation(x.kill_all, x.spec_tag, x.inst_tag);
// conflict with correct spec
for(Integer i = 0; i < valueof(correctSpecPortNum); i = i+1) begin
spec_conflict[i].send;
end
// conflict with the caller of conflictWrongSpec
for(Integer i = 0; i < valueof(conflictWrongSpecPortNum); i = i+1) begin
wrongSpec_conflict[i].send;
end
// conflict with correct spec and conflictWrongSpec
spec_conflict.send;
endrule
Vector#(correctSpecPortNum, Put#(SpecTag)) correctVec = ?;
for(Integer i = 0; i < valueof(correctSpecPortNum); i = i+1) begin
correctVec[i] = (interface Put;
method Action put(SpecTag t) if (!spec_conflict[i]);
method Action put(SpecTag t) if (!spec_conflict);
correctSpecTag[i].wset(t);
endmethod
endinterface);
@@ -103,7 +95,7 @@ module mkGlobalSpecUpdate#(
Vector#(conflictWrongSpecPortNum, Put#(void)) conflictWrongVec = ?;
for(Integer i = 0; i < valueof(conflictWrongSpecPortNum); i = i+1) begin
conflictWrongVec[i] = (interface Put;
method Action put(void x) if (!wrongSpec_conflict[i]);
method Action put(void x) if (!spec_conflict);
noAction;
endmethod
endinterface);

15
src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv
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@@ -51,6 +51,7 @@ import StoreBuffer::*;
import Exec::*;
import FP_Utils::*;
import CacheUtils::*; // For CLoadTags alignment
import RegFile::*; // Just for the interface
// I don't want to export auxiliary functions, so manually export all types
export LdQMemFunc(..);
@@ -439,6 +440,8 @@ interface SplitLSQ;
// Sc/Amo/Fence, and flush L1 cache.
method StQDeqEntry firstSt;
method Action deqSt;
// method for reporting the physical address of an entry used for tracing.
interface Vector#(SupSize, RegFile#(LdStQTag, Addr)) lookupPAddr;
`ifdef TSO_MM
// Kill loads when a cache line is evicted (TSO only)
method Action cacheEvict(LineAddr a);
@@ -1415,6 +1418,16 @@ module mkSplitLSQ(SplitLSQ);
endinterface);
end
RegFile#(LdStQTag, Addr) lookupAPAddr = (interface RegFile;
method Addr sub(LdStQTag t);
case (t) matches
tagged Ld .l: return ld_paddr_deqLd[l];
tagged St .s: return st_paddr_deqSt[s];
endcase
endmethod
method upd = ?;
endinterface);
method ByteOrTagEn getOrigBE(LdStQTag t);
return (case(t) matches
tagged Ld .tag: (ld_byteOrTagEn[tag]);
@@ -2204,6 +2217,8 @@ module mkSplitLSQ(SplitLSQ);
joinActions(map(resetSt, idxVec));
endmethod
interface lookupPAddr = replicate(lookupAPAddr);
`ifdef TSO_MM
method Action cacheEvict(LineAddr lineAddr) if (!wrongSpec_conflict);
if(verbose) $display("[LSQ - cacheEvict] ", fshow(lineAddr));