Merged src_SSITH_P3 and src_SSITH_P3_sim

2020-02-07 21:00:16 +05:30
parent af0b1ef415
commit e35c48efff
295 changed files with 28412 additions and 330732 deletions
--- a/src_SSITH_P3/Verilog_RTL_sim/module_getControlFlow.v
+++ b/src_SSITH_P3/Verilog_RTL_sim/module_getControlFlow.v
@@ -0,0 +1,88 @@
+//
+// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
+//
+//
+//
+//
+// Ports:
+// Name                         I/O  size props
+// getControlFlow                 O   130
+// getControlFlow_dInst           I    72
+// getControlFlow_rVal1           I    64
+// getControlFlow_rVal2           I    64
+// getControlFlow_pc              I    64
+// getControlFlow_ppc             I    64
+// getControlFlow_orig_inst       I    32
+//
+// Combinational paths from inputs to outputs:
+//   (getControlFlow_dInst,
+//    getControlFlow_rVal1,
+//    getControlFlow_rVal2,
+//    getControlFlow_pc,
+//    getControlFlow_ppc,
+//    getControlFlow_orig_inst) -> getControlFlow
+//
+//
+
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+  `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+  `define BSV_RESET_VALUE 1'b1
+  `define BSV_RESET_EDGE posedge
+`else
+  `define BSV_RESET_VALUE 1'b0
+  `define BSV_RESET_EDGE negedge
+`endif
+
+module module_getControlFlow(getControlFlow_dInst,
+			     getControlFlow_rVal1,
+			     getControlFlow_rVal2,
+			     getControlFlow_pc,
+			     getControlFlow_ppc,
+			     getControlFlow_orig_inst,
+			     getControlFlow);
+  // value method getControlFlow
+  input  [71 : 0] getControlFlow_dInst;
+  input  [63 : 0] getControlFlow_rVal1;
+  input  [63 : 0] getControlFlow_rVal2;
+  input  [63 : 0] getControlFlow_pc;
+  input  [63 : 0] getControlFlow_ppc;
+  input  [31 : 0] getControlFlow_orig_inst;
+  output [129 : 0] getControlFlow;
+
+  // signals for module outputs
+  wire [129 : 0] getControlFlow;
+
+  // remaining internal signals
+  wire [63 : 0] x__h51;
+  wire [31 : 0] x__h115;
+  wire aluBr___d9;
+
+  // value method getControlFlow
+  assign getControlFlow =
+	     { getControlFlow_pc,
+	       x__h51,
+	       getControlFlow_dInst[66:64] == 3'd1 && aluBr___d9,
+	       x__h51 != getControlFlow_ppc } ;
+
+  // remaining internal signals
+  module_aluBr instance_aluBr_0(.aluBr_a(getControlFlow_rVal1),
+				.aluBr_b(getControlFlow_rVal2),
+				.aluBr_brFunc(getControlFlow_dInst[48:46]),
+				.aluBr(aluBr___d9));
+  module_brAddrCalc instance_brAddrCalc_1(.brAddrCalc_pc(getControlFlow_pc),
+					  .brAddrCalc_val(getControlFlow_rVal1),
+					  .brAddrCalc_iType(getControlFlow_dInst[71:67]),
+					  .brAddrCalc_imm({ {32{x__h115[31]}},
+							    x__h115 }),
+					  .brAddrCalc_taken(getControlFlow_dInst[66:64] ==
+							    3'd1 &&
+							    aluBr___d9),
+					  .brAddrCalc_orig_inst(getControlFlow_orig_inst),
+					  .brAddrCalc(x__h51));
+  assign x__h115 = getControlFlow_dInst[31:0] ;
+endmodule  // module_getControlFlow
+