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Incremental additions to Tandem Verification trace gen

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This commit is contained in:
rsnikhil
2020-02-06 20:46:26 -05:00
parent c14c9b3e6c
commit af0b1ef415
8 changed files with 21387 additions and 20319 deletions
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2804
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
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38544
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v
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File diff suppressed because it is too large Load Diff

159
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRobRowSynth.v
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@@ -7,7 +7,7 @@
// Ports:
// Name I/O size props
// RDY_write_enq O 1 const
// read_deq O 283
// read_deq O 290
// RDY_read_deq O 1 const
// RDY_setLSQAtCommitNotified O 1 const
// RDY_setExecuted_deqLSQ O 1 const
@@ -26,7 +26,7 @@
// RDY_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// write_enq_x I 283
// write_enq_x I 290
// setExecuted_deqLSQ_cause I 5
// setExecuted_deqLSQ_ld_killed I 3
// setExecuted_doFinishAlu_0_set_csrData I 65
@@ -124,12 +124,12 @@ module mkRobRowSynth(CLK,
input RST_N;
// action method write_enq
input [282 : 0] write_enq_x;
input [289 : 0] write_enq_x;
input EN_write_enq;
output RDY_write_enq;
// value method read_deq
output [282 : 0] read_deq;
output [289 : 0] read_deq;
output RDY_read_deq;
// action method setLSQAtCommitNotified
@@ -189,7 +189,7 @@ module mkRobRowSynth(CLK,
output RDY_correctSpeculation;
// signals for module outputs
wire [282 : 0] read_deq;
wire [289 : 0] read_deq;
wire [63 : 0] getOrigPC, getOrigPredPC;
wire [31 : 0] getOrig_Inst;
wire RDY_correctSpeculation,
@@ -275,6 +275,11 @@ module mkRobRowSynth(CLK,
wire [65 : 0] m_ppc_vaddr_csrData_rl$D_IN;
wire m_ppc_vaddr_csrData_rl$EN;
// register m_rg_dst_reg
reg [6 : 0] m_rg_dst_reg;
wire [6 : 0] m_rg_dst_reg$D_IN;
wire m_rg_dst_reg$EN;
// register m_rob_inst_state_rl
reg m_rob_inst_state_rl;
wire m_rob_inst_state_rl$D_IN, m_rob_inst_state_rl$EN;
@@ -481,19 +486,19 @@ module mkRobRowSynth(CLK,
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q5,
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q6;
reg [1 : 0] CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7;
wire [186 : 0] m_iType_52_CONCAT_m_csr_53_BIT_12_54_CONCAT_IF_ETC___d633;
wire [168 : 0] m_claimed_phy_reg_30_CONCAT_m_trap_dummy2_0_re_ETC___d632;
wire [65 : 0] IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d577;
wire [181 : 0] m_csr_61_BIT_12_62_CONCAT_IF_m_csr_61_BIT_12_6_ETC___d639;
wire [167 : 0] m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d638;
wire [65 : 0] IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d583;
wire [63 : 0] IF_m_ppc_vaddr_csrData_dummy2_0_read__92_AND_m_ETC___d307,
IF_m_ppc_vaddr_csrData_lat_1_whas__74_THEN_m_p_ETC___d206,
IF_m_ppc_vaddr_csrData_lat_3_whas__66_THEN_m_p_ETC___d208,
x__h26637;
x__h26921;
wire [11 : 0] IF_m_spec_bits_lat_1_whas__84_THEN_m_spec_bits_ETC___d290,
bs__h32774,
sb__h32809,
upd__h17926;
bs__h33059,
sb__h33094,
upd__h17960;
wire [4 : 0] IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d153,
x_read_deq_fflags__h25838;
x_read_deq_fflags__h26018;
wire [3 : 0] IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d152,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d131,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d132,
@@ -522,11 +527,11 @@ module mkRobRowSynth(CLK,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95,
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d674,
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d682,
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d681,
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d689,
NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_93_O_ETC___d302,
m_rob_inst_state_dummy2_0_read__83_AND_m_rob_i_ETC___d594,
m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536;
m_rob_inst_state_dummy2_0_read__89_AND_m_rob_i_ETC___d600,
m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543;
// action method write_enq
assign RDY_write_enq = 1'd1 ;
@@ -537,7 +542,9 @@ module mkRobRowSynth(CLK,
assign read_deq =
{ m_pc,
m_orig_inst,
m_iType_52_CONCAT_m_csr_53_BIT_12_54_CONCAT_IF_ETC___d633 } ;
m_rg_dst_reg,
m_iType,
m_csr_61_BIT_12_62_CONCAT_IF_m_csr_61_BIT_12_6_ETC___d639 } ;
assign RDY_read_deq = 1'd1 ;
// action method setLSQAtCommitNotified
@@ -590,7 +597,7 @@ module mkRobRowSynth(CLK,
assign RDY_getOrig_Inst = 1'd1 ;
// value method dependsOn_wrongSpec
assign dependsOn_wrongSpec = bs__h32774[dependsOn_wrongSpec_tag] ;
assign dependsOn_wrongSpec = bs__h33059[dependsOn_wrongSpec_tag] ;
assign RDY_dependsOn_wrongSpec = 1'd1 ;
// action method correctSpeculation
@@ -916,11 +923,11 @@ module mkRobRowSynth(CLK,
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
// register m_orig_inst
assign m_orig_inst$D_IN = write_enq_x[218:187] ;
assign m_orig_inst$D_IN = write_enq_x[225:194] ;
assign m_orig_inst$EN = EN_write_enq ;
// register m_pc
assign m_pc$D_IN = write_enq_x[282:219] ;
assign m_pc$D_IN = write_enq_x[289:226] ;
assign m_pc$EN = EN_write_enq ;
// register m_ppc_vaddr_csrData_rl
@@ -933,6 +940,10 @@ module mkRobRowSynth(CLK,
IF_m_ppc_vaddr_csrData_lat_3_whas__66_THEN_m_p_ETC___d208 } ;
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
// register m_rg_dst_reg
assign m_rg_dst_reg$D_IN = write_enq_x[193:187] ;
assign m_rg_dst_reg$EN = EN_write_enq ;
// register m_rob_inst_state_rl
assign m_rob_inst_state_rl$D_IN =
EN_write_enq ?
@@ -944,7 +955,7 @@ module mkRobRowSynth(CLK,
// register m_spec_bits_rl
assign m_spec_bits_rl$D_IN =
EN_correctSpeculation ?
upd__h17926 :
upd__h17960 :
IF_m_spec_bits_lat_1_whas__84_THEN_m_spec_bits_ETC___d290 ;
assign m_spec_bits_rl$EN = 1'd1 ;
@@ -1176,7 +1187,7 @@ module mkRobRowSynth(CLK,
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d67 ?
4'd3 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d148) ;
assign IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d577 =
assign IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d583 =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_93_O_ETC___d302 ||
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ?
{ 2'd0,
@@ -1306,32 +1317,48 @@ module mkRobRowSynth(CLK,
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd7 :
m_trap_rl[3:0] == 4'd7) ;
assign NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d674 =
assign NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d681 =
m_csr[12] != setExecuted_doFinishAlu_0_set_csrData[64] ;
assign NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d682 =
assign NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d689 =
m_csr[12] != setExecuted_doFinishAlu_1_set_csrData[64] ;
assign NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_93_O_ETC___d302 =
!m_ppc_vaddr_csrData_dummy2_0$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_1$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_2$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_3$Q_OUT ;
assign bs__h32774 =
assign bs__h33059 =
(m_spec_bits_dummy2_0$Q_OUT && m_spec_bits_dummy2_1$Q_OUT &&
m_spec_bits_dummy2_2$Q_OUT) ?
m_spec_bits_rl :
12'd0 ;
assign m_claimed_phy_reg_30_CONCAT_m_trap_dummy2_0_re_ETC___d632 =
{ m_claimed_phy_reg,
m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536,
assign m_csr_61_BIT_12_62_CONCAT_IF_m_csr_61_BIT_12_6_ETC___d639 =
{ m_csr[12],
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
m_claimed_phy_reg,
m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d638 } ;
assign m_rob_inst_state_dummy2_0_read__89_AND_m_rob_i_ETC___d600 =
m_rob_inst_state_dummy2_0$Q_OUT &&
m_rob_inst_state_dummy2_1$Q_OUT &&
m_rob_inst_state_dummy2_2$Q_OUT &&
m_rob_inst_state_dummy2_3$Q_OUT &&
m_rob_inst_state_dummy2_4$Q_OUT &&
m_rob_inst_state_dummy2_5$Q_OUT &&
m_rob_inst_state_rl ;
assign m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543 =
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5] ;
assign m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d638 =
{ m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543,
m_trap_rl[4],
m_trap_rl[4] ?
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1 :
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2,
x__h26637,
IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d577,
x_read_deq_fflags__h25838,
x__h26921,
IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__92_9_ETC___d583,
x_read_deq_fflags__h26018,
m_will_dirty_fpu_state,
m_rob_inst_state_dummy2_0_read__83_AND_m_rob_i_ETC___d594,
m_rob_inst_state_dummy2_0_read__89_AND_m_rob_i_ETC___d600,
m_lsqTag,
m_ldKilled_dummy2_0$Q_OUT && m_ldKilled_dummy2_1$Q_OUT &&
m_ldKilled_rl[2],
@@ -1347,35 +1374,18 @@ module mkRobRowSynth(CLK,
m_nonMMIOStDone_dummy2_1$Q_OUT &&
m_nonMMIOStDone_rl,
m_epochIncremented,
bs__h32774 } ;
assign m_iType_52_CONCAT_m_csr_53_BIT_12_54_CONCAT_IF_ETC___d633 =
{ m_iType,
m_csr[12],
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
m_claimed_phy_reg_30_CONCAT_m_trap_dummy2_0_re_ETC___d632 } ;
assign m_rob_inst_state_dummy2_0_read__83_AND_m_rob_i_ETC___d594 =
m_rob_inst_state_dummy2_0$Q_OUT &&
m_rob_inst_state_dummy2_1$Q_OUT &&
m_rob_inst_state_dummy2_2$Q_OUT &&
m_rob_inst_state_dummy2_3$Q_OUT &&
m_rob_inst_state_dummy2_4$Q_OUT &&
m_rob_inst_state_dummy2_5$Q_OUT &&
m_rob_inst_state_rl ;
assign m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536 =
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5] ;
assign sb__h32809 =
bs__h33059 } ;
assign sb__h33094 =
m_spec_bits_dummy2_2$Q_OUT ?
IF_m_spec_bits_lat_1_whas__84_THEN_m_spec_bits_ETC___d290 :
12'd0 ;
assign upd__h17926 = sb__h32809 & correctSpeculation_mask ;
assign x__h26637 =
assign upd__h17960 = sb__h33094 & correctSpeculation_mask ;
assign x__h26921 =
(m_tval_dummy2_0$Q_OUT && m_tval_dummy2_1$Q_OUT &&
m_tval_dummy2_2$Q_OUT) ?
m_tval_rl :
64'd0 ;
assign x_read_deq_fflags__h25838 =
assign x_read_deq_fflags__h26018 =
(m_fflags_dummy2_0$Q_OUT && m_fflags_dummy2_1$Q_OUT) ?
m_fflags_rl :
5'd0 ;
@@ -1611,6 +1621,8 @@ module mkRobRowSynth(CLK,
if (m_lsqTag$EN) m_lsqTag <= `BSV_ASSIGNMENT_DELAY m_lsqTag$D_IN;
if (m_orig_inst$EN) m_orig_inst <= `BSV_ASSIGNMENT_DELAY m_orig_inst$D_IN;
if (m_pc$EN) m_pc <= `BSV_ASSIGNMENT_DELAY m_pc$D_IN;
if (m_rg_dst_reg$EN)
m_rg_dst_reg <= `BSV_ASSIGNMENT_DELAY m_rg_dst_reg$D_IN;
if (m_will_dirty_fpu_state$EN)
m_will_dirty_fpu_state <= `BSV_ASSIGNMENT_DELAY
m_will_dirty_fpu_state$D_IN;
@@ -1634,6 +1646,7 @@ module mkRobRowSynth(CLK,
m_orig_inst = 32'hAAAAAAAA;
m_pc = 64'hAAAAAAAAAAAAAAAA;
m_ppc_vaddr_csrData_rl = 66'h2AAAAAAAAAAAAAAAA;
m_rg_dst_reg = 7'h2A;
m_rob_inst_state_rl = 1'h0;
m_spec_bits_rl = 12'hAAA;
m_trap_rl = 6'h2A;
@@ -1651,39 +1664,39 @@ module mkRobRowSynth(CLK,
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d674)
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d681)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d674)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 210, column 60\ncsr valid should match");
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d681)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 212, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d674)
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d681)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d682)
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d689)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d682)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 210, column 60\ncsr valid should match");
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d689)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 212, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_53_BIT_12_54_EQ_setExecuted_doFinish_ETC___d682)
NOT_m_csr_61_BIT_12_62_EQ_setExecuted_doFinish_ETC___d689)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536)
m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 322, column 52\ncannot have trap");
m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 326, column 52\ncannot have trap");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__31_AND_m_trap_dummy2_1_r_ETC___d536)
m_trap_dummy2_0_read__38_AND_m_trap_dummy2_1_r_ETC___d543)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
@@ -1694,7 +1707,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
setExecuted_doFinishMem_non_mmio_st_done)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 237, column 18\ncannot both be true");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 239, column 18\ncannot both be true");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
@@ -1709,7 +1722,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
m_iType != 5'd5)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 241, column 35\nmust be St");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 243, column 35\nmust be St");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
@@ -1720,7 +1733,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 285, column 40\nld killed must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 288, column 40\nld killed must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1728,7 +1741,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 286, column 48\nmem access at commit must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 289, column 48\nmem access at commit must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1736,7 +1749,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 287, column 42\nlsq notified must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 290, column 42\nlsq notified must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1744,7 +1757,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 288, column 36\nnon mmio st must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 291, column 36\nnon mmio st must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13]) $finish(32'd0);
end

3
src_Core/Core/Trace_Data2.bsv
View File

@@ -24,9 +24,10 @@ import ReorderBuffer :: *;
// add to the critical path or scheduling requirements of CommitStage.
typedef struct {
Bit #(64) serialnum; // instruction serial number
Bit #(64) serial_num; // TV message serial number
Addr pc;
Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
IType iType;
Maybe #(CSR) csr;
Maybe #(Trap) trap;

147
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
View File

@@ -4,7 +4,7 @@ package Trace_Data2_to_Trace_Data;
// ================================================================
// This package defines a module to transform a stream of Trace_Data2
// to a stream of (serialnum, Trace_Data)
// to a stream of (serial_num, Trace_Data)
// ================================================================
// BSV library imports
@@ -35,11 +35,10 @@ import Trace_Data2 :: *;
// ================================================================
interface Trace_Data2_to_Trace_Data_IFC;
method Action init;
// From Toooba's CommitStage
interface Put #(Trace_Data2) in;
// To Trace Encoder
interface Get #(Tuple2 #(Bit #(64), Trace_Data)) out;
endinterface
@@ -48,7 +47,7 @@ endinterface
(* synthesize *)
module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
Integer verbosity = 0; // for debugging
Integer verbosity = 1; // for debugging
// Input stream
FIFOF #(Trace_Data2) f_in <- mkFIFOF;
@@ -57,84 +56,154 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
FIFOF #(Tuple2 #(Bit #(64), Trace_Data)) f_out <- mkFIFOF;
// ================================================================
// Transformer: Trace_Data2 -> (serialnum, Trace_Data)
// Transformer: Trace_Data2 -> (serial_num, Trace_Data)
function ActionValue #(Tuple2 #(Bit #(64), Trace_Data)) fav_xform (Trace_Data2 td2);
function ActionValue #(Tuple2 #(Bit #(64), Trace_Data)) fav_td2_to_td (Trace_Data2 td2);
actionvalue
let serialnum = td2.serialnum;
Trace_Data td = ?;
ISize isize = ((td2.orig_inst [1:0] == 2'b11) ? ISIZE32BIT : ISIZE16BIT);
let serial_num = td2.serial_num;
Trace_Data td = ?;
ISize isize = ((td2.orig_inst [1:0] == 2'b11) ? ISIZE32BIT : ISIZE16BIT);
Addr fall_thru_PC = td2.pc + ((td2.orig_inst [1:0] == 2'b11) ? 4 : 2);
if ( (td2.iType == Alu)
|| (td2.iType == J)
|| (td2.iType == Jr)
|| (td2.iType == Auipc))
td = mkTrace_I_RD (td2.pc,
Bit #(5) gpr_rd = 0;
if (td2.dst matches tagged Valid (tagged Gpr .r)) gpr_rd = r;
if (serial_num == 0)
td = mkTrace_RESET;
else if (td2.ppc_vaddr_csrData matches tagged PPC .target_addr
&&& (td2.iType == Br))
td = mkTrace_OTHER (target_addr, isize, td2.orig_inst);
else if (td2.ppc_vaddr_csrData matches tagged PPC .target_addr
&&& ( (td2.iType == J)
|| (td2.iType == Jr)))
td = mkTrace_I_RD (target_addr,
isize,
td2.orig_inst,
0, // TODO: rd
gpr_rd,
0); // TODO: return-pc
else if ( (td2.iType == Alu)
|| (td2.iType == Auipc))
td = mkTrace_I_RD (fall_thru_PC,
isize,
td2.orig_inst,
gpr_rd,
0); // TODO: rd_val
else if ( (td2.iType == Br)
|| (td2.iType == Fence)
else if (td2.dst matches tagged Valid (tagged Fpu .fpr_rd)
&&& (td2.iType == Fpu))
td = mkTrace_F_FRD (fall_thru_PC,
isize,
td2.orig_inst,
fpr_rd,
?, // TODO: rdval
?, // TODO: Bit#(5) fflags
?); // TODO: mstatus)
else if (td2.iType == Fpu)
td = mkTrace_F_GRD (fall_thru_PC,
isize,
td2.orig_inst,
gpr_rd,
?, // TODO: rdval
?, // TODO: Bit#(5) fflags
?); // TODO: mstatus)
else if (td2.ppc_vaddr_csrData matches tagged VAddr .eaddr
&&& (td2.iType == Ld))
td = mkTrace_I_LOAD (fall_thru_PC,
isize,
td2.orig_inst,
gpr_rd,
?, // TODO: rd_val
eaddr);
else if (td2.ppc_vaddr_csrData matches tagged VAddr .eaddr
&&& (td2.iType == St))
td = mkTrace_I_STORE (fall_thru_PC,
?, // TODO: funct3,
isize,
td2.orig_inst,
?, // store-value
eaddr);
else if (td2.ppc_vaddr_csrData matches tagged CSRData .csr_data
&&& (td2.iType == Csr))
begin
Bool csr_valid = False;
CSR_Addr csr_addr = 0;
if (td2.csr matches tagged Valid .c) begin
csr_valid = True;
csr_addr = pack (c);
end
td = mkTrace_CSRRX (fall_thru_PC,
isize,
td2.orig_inst,
gpr_rd,
?, // TODO: rdval
csr_valid,
csr_addr,
csr_data);
end
else if ( (td2.iType == Fence)
|| (td2.iType == FenceI)
|| (td2.iType == SFence)
|| (td2.iType == Ecall)
|| (td2.iType == Ebreak)
|| (td2.iType == Mret)
|| (td2.iType == Sret))
td = mkTrace_OTHER (td2.pc, isize, td2.orig_inst);
td = mkTrace_OTHER (fall_thru_PC, isize, td2.orig_inst);
else if ( (td2.iType == Amo)
|| (td2.iType == Lr)
|| (td2.iType == Sc))
td = mkTrace_AMO (td2.pc,
td = mkTrace_AMO (fall_thru_PC,
0, // TODO: funct3
isize,
td2.orig_inst,
0, // TODO: rd
gpr_rd,
0, // TODO: rd_val
0, // TODO: rs2_val
0 // TODO: eaddr
);
else if ( (td2.iType == Unsupported)
|| (td2.iType == Nop)
|| (td2.iType == Interrupt))
td = mkTrace_OTHER (fall_thru_PC, isize, td2.orig_inst);
else begin
if (verbosity != 0) begin
$display (" fav_xform: TBD: Using mkTrace_I_RD for now");
if (verbosity > 0) begin
$display (" fav_td2_to_td: TBD: Unknown iType: Using mkTrace_OTHER for now");
$display (" ", fshow (td2));
end
td = mkTrace_I_RD (td2.pc,
isize,
td2.orig_inst,
0, // TODO: rd
0); // TODO: rd_val
td = mkTrace_OTHER (fall_thru_PC, isize, td2.orig_inst);
end
return tuple2 (serialnum, td);
return tuple2 (serial_num, td);
endactionvalue
endfunction
// ================================================================
// RULES
rule rl_xform;
rule rl_td2_to_td;
Trace_Data2 td2 <- pop (f_in);
if (verbosity != 0)
$display ("%0d: %m.rl_xform: serialnum:%0d PC:0x%0h instr:0x%08h",
cur_cycle, td2.serialnum, td2.pc, td2.orig_inst,
if (verbosity > 1)
$display ("%0d: %m.rl_td2_to_td: serial_num:%0d PC:0x%0h instr:0x%08h",
cur_cycle, td2.serial_num, td2.pc, td2.orig_inst,
" iType:", fshow (td2.iType));
match { .serialnum, .td } <- fav_xform (td2);
f_out.enq (tuple2 (serialnum, td));
match { .serial_num, .td } <- fav_td2_to_td (td2);
f_out.enq (tuple2 (serial_num, td));
endrule
// ================================================================
// INTERFACE
method Action init;
f_in.clear;
f_out.clear;
endmethod
interface in = toPut (f_in);
interface out = toGet (f_out);
endmodule

40
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -158,20 +158,21 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Integer verbosity = 1; // Bluespec: for lightweight verbosity trace
// Used to inform tandem-verifier about program order.
// 0 is used to indicate we've just come out of reset
// TODO: we could use fewer bits and allow and recognize wraparound.
Reg #(Bit #(64)) rg_serialnum <- mkReg (0);
Reg #(Bit #(64)) rg_serial_num <- mkReg (0);
`ifdef INCLUDE_GDB_CONTROL
Reg #(Run_State) rg_run_state <- mkReg (RUN_STATE_RUNNING);
`endif
`ifdef INCLUDE_TANDEM_VERIF
function Action fa_to_TV (Bit #(64) serialnum, ToReorderBuffer deq_data, Integer way);
function Action fa_to_TV (Bit #(64) serial_num, ToReorderBuffer deq_data, Integer way);
action
let x = Trace_Data2 {serialnum: serialnum,
let x = Trace_Data2 {serial_num: serial_num,
pc: deq_data.pc,
orig_inst: deq_data.orig_inst,
dst: deq_data.dst,
iType: deq_data.iType,
csr: deq_data.csr,
trap: deq_data.trap,
@@ -182,6 +183,14 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
inIfc.v_to_TV [way].put (x);
endaction
endfunction
Reg #(Bool) rg_just_after_reset <- mkReg (True);
rule rl_send_tv_reset (rg_just_after_reset);
fa_to_TV (0, ?, 0);
rg_just_after_reset <= False;
rg_serial_num <= 1;
endrule
`endif
// func units
@@ -467,7 +476,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
commitTrap <= commitTrap_val;
if (verbosity >= 1) begin
$display ("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst,
$display ("instret:%0d PC:0x%0h instr:0x%08h", rg_serial_num, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitTrap]");
end
if (verbose) begin
@@ -476,9 +485,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
fa_to_TV (rg_serial_num, x, 0);
`endif
rg_serialnum <= rg_serialnum + 1;
rg_serial_num <= rg_serial_num + 1;
// flush everything. Only increment epoch and stall fetch when we haven
// not done it yet (we may have already done them at rename stage)
@@ -629,14 +638,14 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if(verbose) $display("[doCommitSystemInst] ", fshow(x));
if (verbosity >= 1) begin
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst,
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serial_num, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitSystemInst]");
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
fa_to_TV (rg_serial_num, x, 0);
`endif
rg_serialnum <= rg_serialnum + 1;
rg_serial_num <= rg_serial_num + 1;
// we claim a phy reg for every inst, so commit its renaming
regRenamingTable.commit[0].commit;
@@ -798,13 +807,13 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x));
if (verbosity >= 1) begin
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum + instret, x.pc, x.orig_inst,
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serial_num + instret, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitNormalInst [%0d]]", i);
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum + instret, x, i);
fa_to_TV (rg_serial_num + instret, x, i);
`endif
instret = instret + 1;
instret = instret + 1;
// inst can be committed, deq it
rob.deqPort[i].deq;
@@ -857,7 +866,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
end
end
rg_serialnum <= rg_serialnum + instret;
rg_serial_num <= rg_serial_num + instret;
// write FPU csr
if(csrf.fpuInstNeedWr(fflags, will_dirty_fpu_state)) begin
@@ -904,6 +913,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
`endif
endrule
// ================================================================
// INTERFACE
method Data getPerf(ComStagePerfType t);
return (case(t)
`ifdef PERF_COUNT

5
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -347,6 +347,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
// just place it in the reorder buffer
let y = ToReorderBuffer{pc: pc,
orig_inst: orig_inst,
dst: arch_regs.dst,
iType: dInst.iType,
csr: dInst.csr,
claimed_phy_reg: False, // no renaming is done
@@ -446,6 +447,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
let x = fetchStage.pipelines[0].first;
let pc = x.pc;
let orig_inst = x.orig_inst;
let dst = x.regs.dst;
let ppc = x.ppc;
let main_epoch = x.main_epoch;
let dpTrain = x.dpTrain;
@@ -520,6 +522,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
RobInstState rob_inst_state = to_exec ? NotDone : Executed;
let y = ToReorderBuffer{pc: pc,
orig_inst: orig_inst,
dst: arch_regs.dst,
iType: dInst.iType,
csr: dInst.csr,
claimed_phy_reg: True, // XXX we always claim a free reg in rename
@@ -685,6 +688,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
RobInstState rob_inst_state = NotDone; // mem inst always needs execution
let y = ToReorderBuffer{pc: pc,
orig_inst: orig_inst,
dst: arch_regs.dst,
iType: dInst.iType,
csr: dInst.csr,
claimed_phy_reg: True, // XXX we always claim a free reg in rename
@@ -1037,6 +1041,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
let y = ToReorderBuffer{pc: pc,
orig_inst: orig_inst,
dst: arch_regs.dst,
iType: dInst.iType,
csr: dInst.csr,
claimed_phy_reg: True, // XXX we always claim a free reg in rename

4
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -47,6 +47,7 @@ typedef union tagged {
typedef struct {
Addr pc;
Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
IType iType;
Maybe#(CSR) csr;
Bool claimed_phy_reg; // whether we need to commmit renaming
@@ -170,6 +171,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Reg#(Addr) pc <- mkRegU;
Reg #(Bit #(32)) orig_inst <- mkRegU;
Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkRegU;
Reg#(IType) iType <- mkRegU;
Reg#(Maybe#(CSR)) csr <- mkRegU;
Reg#(Bool) claimed_phy_reg <- mkRegU;
@@ -259,6 +261,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
method Action write_enq(ToReorderBuffer x);
pc <= x.pc;
orig_inst <= x.orig_inst;
rg_dst_reg <= x.dst;
iType <= x.iType;
csr <= x.csr;
claimed_phy_reg <= x.claimed_phy_reg;
@@ -292,6 +295,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
return ToReorderBuffer {
pc: pc,
orig_inst: orig_inst,
dst: rg_dst_reg,
iType: iType,
csr: csr,
claimed_phy_reg: claimed_phy_reg,