Plumb through info on whether a load is capWidth to the TLB

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -114,6 +114,7 @@ typedef struct {
 `endif
     Bool misaligned;
     Bool capStore;
+    Bool capWidthLoad;
     Bool allowCap;
     Maybe#(CSR_XCapCause) capException;
     Maybe#(BoundsCheck) check;
@@ -166,7 +167,8 @@ module mkDTlbSynth(DTlbSynth);
                         St, Sc, Amo: True;
                         default: False;
                     endcase),
-            cap: x.capStore
+            capStore: x.capStore,
+            capWidthLoad: x.capWidthLoad
         };
     endfunction
     let m <- mkDTlb(getTlbReq);
@@ -576,6 +578,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
 `endif
                 misaligned: memAddrMisaligned(getAddr(vaddr), origBE),
                 capStore: isValidCap(data) && origBE == DataMemAccess(unpack(~0)),
+                capWidthLoad: origBE == DataMemAccess(unpack(~0)),
                 allowCap: getHardPerms(x.rVal1).permitLoadCap,
                 capException: capChecksMem(x.rVal1, x.rVal2, x.cap_checks, x.mem_func, origBE),
                 check: prepareBoundsCheck(x.rVal1, x.rVal2, almightyCap/*ToDo: pcc*/,

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -286,13 +286,18 @@ module mkDTlb#(
         end
         else if(pRs.entry matches tagged Valid .en) begin
             // check permission
+            $display("dPRs: vm_info: ", fshow(vm_info),
+                     "      en     : ", fshow(en),
+                     "      r      : ", fshow(r)
+                     );
             let permCheck = hasVMPermission(vm_info,
                                             en.pteType,
                                             en.pteUpperType,
                                             en.ppn,
                                             en.level,
                                             r.write ? DataStore : DataLoad,
-                                            r.cap);
+                                            r.capStore,
+                                            r.capWidthLoad);
             if (permCheck.allowed) begin
                 // fill TLB, and record resp
                 tlb.addEntry(en);
@@ -471,13 +476,18 @@ module mkDTlb#(
                 // TLB hit
                 let entry = trans_result.entry;
                 // check permission
+            $display("procReq: vm_info: ", fshow(vm_info),
+                     "         en     : ", fshow(entry),
+                     "         r      : ", fshow(r)
+                     );
                 let permCheck = hasVMPermission(vm_info,
                                                 entry.pteType,
                                                 entry.pteUpperType,
                                                 entry.ppn,
                                                 entry.level,
                                                 r.write ? DataStore : DataLoad,
-                                                r.cap);
+                                                r.capStore,
+                                                r.capWidthLoad);
                 $display("Permission check output 2: ", fshow(permCheck));
                 if (permCheck.allowed) begin
                     // update TLB replacement info

src_Core/RISCY_OOO/procs/lib/ITlb.bsv

@@ -195,6 +195,7 @@ module mkITlb(ITlb::ITlb);
                                en.ppn,
                                en.level,
                                InstFetch,
+                               False,
                                False).allowed) begin
                 // fill TLB and resp to proc
                 tlb.addEntry(en);
@@ -312,6 +313,7 @@ module mkITlb(ITlb::ITlb);
                                            entry.ppn,
                                            entry.level,
                                            InstFetch,
+                                           False,
                                            False).allowed) begin
                             // update replacement info
                             tlb.updateRepByHit(trans_result.index);

src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv

@@ -31,7 +31,8 @@ import ProcTypes::*;
 typedef struct{
     Addr  addr;
     Bool  write;
-    Bool  cap;
+    Bool  capStore;
+    Bool  capWidthLoad;
 } TlbReq deriving(Eq, Bits, FShow);
 typedef Tuple3#(Addr, Maybe#(Exception), Bool) TlbResp;
 
@@ -190,7 +191,8 @@ function TlbPermissionCheck hasVMPermission(
     VMInfo vm_info,
     PTEType pte_type, PTEUpperType pte_upper_type,
      Ppn ppn, PageWalkLevel level,
-    TlbAccessType access, Bool cap
+    TlbAccessType access,
+    Bool capStore, Bool capWidthLoad
 );
     // try to find any page fault
     Bool fault = False;
@@ -247,7 +249,7 @@ function TlbPermissionCheck hasVMPermission(
                 !(pte_type.executable && vm_info.exeReadable)) begin
                 fault = True;
             end
-            if (cap) begin
+            if (capWidthLoad) begin
                 if (!fault) excCode = excLoadCapPageFault;
                 // load traps if page not cap readable and using cap_read_mod set
                 if (!pte_upper_type.cap_readable && pte_upper_type.cap_read_mod) begin
@@ -267,7 +269,7 @@ function TlbPermissionCheck hasVMPermission(
             if(!(pte_type.readable && pte_type.writable)) begin
                 fault = True;
             end
-            else if(cap && !pte_upper_type.cap_writable) begin
+            else if(capStore && !pte_upper_type.cap_writable) begin
                 if (!fault) excCode = excStoreCapPageFault;
                 fault = True;
             end
@@ -281,7 +283,7 @@ function TlbPermissionCheck hasVMPermission(
 
     if (!fault) begin
         // check if accessed or dirty bit needs to be set
-        if(cap && access == DataStore && !pte_upper_type.cap_dirty) begin
+        if(capStore && access == DataStore && !pte_upper_type.cap_dirty) begin
             ret.allowed = False;
             ret.excCode = excStoreCapPageFault;
         end