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Revert "Provide opt-in wedge debugging info"

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This reverts commit 68d3bd484e.
This commit is contained in:
Peter Rugg
2021-01-19 22:00:16 +00:00
parent 20f1ddf587
commit e8487e2a1c
9 changed files with 2 additions and 136 deletions
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12
src_Core/CPU/Core.bsv
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@@ -205,13 +205,6 @@ interface Core;
interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
`endif
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Tuple2#(CapMem, Bit#(32)) debugLastInst;
(* always_enabled *)
method Tuple2#(CapMem, Bit#(32)) debugNextInst;
`endif
`ifdef PERFORMANCE_MONITORING
method Action events_llc(EventsCache events);
method Action events_tgc(EventsCache events);
@@ -1517,11 +1510,6 @@ module mkCore#(CoreId coreId)(Core);
interface v_to_TV = map (toGet, v_f_to_TV);
`endif
`ifdef DEBUG_WEDGE
method Tuple2#(CapMem, Bit#(32)) debugLastInst = commitStage.debugLastInst;
method Tuple2#(CapMem, Bit#(32)) debugNextInst = rob.debugNextInst;
`endif
`ifdef PERFORMANCE_MONITORING
method events_llc = events_llc_reg._write;
method events_tgc = events_tgc_reg._write;

10
src_Core/CPU/Proc.bsv
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@@ -104,11 +104,6 @@ import ProcTypes :: *;
import Trace_Data2 :: *;
`endif
`ifdef DEBUG_WEDGE
import CHERICap :: *;
import CHERICC_Fat :: *;
`endif
// ================================================================
(* synthesize *)
@@ -351,11 +346,6 @@ module mkProc (Proc_IFC);
interface v_to_TV = core [0].v_to_TV;
`endif
`ifdef DEBUG_WEDGE
method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst;
method Tuple2#(CapMem, Bit#(32)) hart0_next_inst = core[0].debugNextInst;
`endif
`ifdef PERFORMANCE_MONITORING
method events_tgc = events_tgc_reg._write;
`endif

12
src_Core/CPU/Proc_IFC.bsv
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@@ -47,11 +47,6 @@ import Trace_Data2 :: *;
import ProcTypes :: *;
`endif
`ifdef DEBUG_WEDGE
import CHERICap :: *;
import CHERICC_Fat :: *;
`endif
// ================================================================
// CPU interface
@@ -134,13 +129,6 @@ interface Proc_IFC;
interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
`endif
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Tuple2#(CapMem, Bit#(32)) hart0_last_inst;
(* always_enabled *)
method Tuple2#(CapMem, Bit#(32)) hart0_next_inst;
`endif
`ifdef PERFORMANCE_MONITORING
method Action events_tgc(EventsCache events);
`endif

5
src_Core/Core/CoreW.bsv
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@@ -242,11 +242,6 @@ module mkCoreW #(Reset dm_power_on_reset)
mkConnection (debug_module.hart0_client_run_halt, proc.hart0_run_halt_server);
mkConnection (debug_module.hart0_get_other_req, proc.hart0_put_other_req);
`ifdef DEBUG_WEDGE
mkConnection (proc.hart0_last_inst, debug_module.hart0_last_inst);
mkConnection (proc.hart0_next_inst, debug_module.hart0_next_inst);
`endif
`endif
`ifdef INCLUDE_TANDEM_VERIF

22
src_Core/Debug_Module/DM_Common.bsv
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@@ -22,7 +22,7 @@ package DM_Common;
typedef Bit #(7) DM_Addr;
DM_Addr max_DM_Addr = 'h7F;
DM_Addr max_DM_Addr = 'h5F;
typedef Bit #(32) DM_Word;
@@ -79,26 +79,6 @@ DM_Addr dm_addr_sbdata1 = 'h3d;
DM_Addr dm_addr_sbdata2 = 'h3e;
DM_Addr dm_addr_sbdata3 = 'h3f;
// ----------------
// Custom registers
DM_Addr dm_addr_custom0 = 'h70;
DM_Addr dm_addr_custom1 = 'h71;
DM_Addr dm_addr_custom2 = 'h72;
DM_Addr dm_addr_custom3 = 'h73;
DM_Addr dm_addr_custom4 = 'h74;
DM_Addr dm_addr_custom5 = 'h75;
DM_Addr dm_addr_custom6 = 'h76;
DM_Addr dm_addr_custom7 = 'h77;
DM_Addr dm_addr_custom8 = 'h78;
DM_Addr dm_addr_custom9 = 'h79;
DM_Addr dm_addr_custom10 = 'h7a;
DM_Addr dm_addr_custom11 = 'h7b;
DM_Addr dm_addr_custom12 = 'h7c;
DM_Addr dm_addr_custom13 = 'h7d;
DM_Addr dm_addr_custom14 = 'h7e;
DM_Addr dm_addr_custom15 = 'h7f;
// ================================================================
function Fmt fshow_dm_addr (DM_Addr dm_addr);

61
src_Core/Debug_Module/Debug_Module.bsv
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@@ -91,12 +91,6 @@ import DM_Run_Control :: *;
import DM_Abstract_Commands :: *;
import DM_System_Bus :: *;
`ifdef DEBUG_WEDGE
import ConfigReg :: *;
import CHERICap :: *;
import CHERICC_Fat :: *;
`endif
// ================================================================
export DM_Common :: *;
@@ -132,15 +126,6 @@ interface Debug_Module_IFC;
// CSR access
interface Client #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_client;
// Optional debug from commit stage and ROB
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
(* always_enabled *)
method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
`endif
// ----------------
// Facing Platform
@@ -169,13 +154,6 @@ module mkDebug_Module (Debug_Module_IFC);
FIFO#(DM_Addr) f_read_addr <- mkFIFO1;
`ifdef DEBUG_WEDGE
Reg #(CapMem) rg_last_pcc <- mkConfigReg (unpack (0));
Reg #(Bit #(32)) rg_last_inst <- mkConfigReg (0);
Reg #(CapMem) rg_next_pcc <- mkConfigReg (unpack (0));
Reg #(Bit #(32)) rg_next_inst <- mkConfigReg (0);
`endif
// ================================================================
// Reset all three parts when dm_run_control.dmactive is low
@@ -250,32 +228,6 @@ module mkDebug_Module (Debug_Module_IFC);
dm_word <- dm_system_bus.av_read (dm_addr);
`ifdef DEBUG_WEDGE
else if (dm_addr == dm_addr_custom0)
dm_word = getAddr (rg_last_pcc) [31:0];
else if (dm_addr == dm_addr_custom1)
dm_word = getAddr (rg_last_pcc) [63:32];
else if (dm_addr == dm_addr_custom2)
dm_word = rg_last_inst;
else if (dm_addr == dm_addr_custom3)
dm_word = getAddr (rg_next_pcc) [31:0];
else if (dm_addr == dm_addr_custom4)
dm_word = getAddr (rg_next_pcc) [63:32];
else if (dm_addr == dm_addr_custom5)
dm_word = rg_next_inst;
`endif
else begin
// TODO: set error status?
dm_word = 0;
@@ -363,19 +315,6 @@ module mkDebug_Module (Debug_Module_IFC);
// CSR access
interface Client hart0_csr_mem_client = dm_abstract_commands.hart0_csr_mem_client;
// Optional debug from commit stage
`ifdef DEBUG_WEDGE
method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
rg_last_pcc <= tpl_1 (pcc_inst);
rg_last_inst <= tpl_2 (pcc_inst);
endmethod
method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
rg_next_pcc <= tpl_1 (pcc_inst);
rg_next_inst <= tpl_2 (pcc_inst);
endmethod
`endif
// ----------------
// Facing Platform

11
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -655,11 +655,6 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum
method Bool isFull_ehrPort0;
interface ROB_SpeculationUpdate specUpdate;
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Tuple2#(CapMem, Bit#(32)) debugNextInst;
`endif
endinterface
typedef struct {
@@ -1312,10 +1307,4 @@ module mkSupReorderBuffer#(
end
endmethod
endinterface
`ifdef DEBUG_WEDGE
method Tuple2#(CapMem, Bit#(32)) debugNextInst;
return tuple2(fifo_first[0].pc, fifo_first[0].orig_inst);
endmethod
`endif
endmodule

3
src_SSITH_P3/Makefile
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@@ -40,9 +40,6 @@ BSC_COMPILATION_FLAGS += \
-D BRVF_TRACE \
-D XILINX_BSCAN -D JTAG_TAP
# Enable to expose last and next instruction info as DMI registers
#BSC_COMPILATION_FLAGS += -D DEBUG_WEDGE
# Synth only BSC_COMPILATION_FLAGS
SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P

2
src_SSITH_P3/src_BSV/JtagTap.bsv
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@@ -13,7 +13,7 @@ import PowerOnReset ::*;
import ClockHacks ::*;
import Giraffe_IFC ::*;
typedef 7 ABITS;
typedef 6 ABITS;
`ifdef XILINX_BSCAN
`ifdef XILINX_XCVU095
typedef 6 IR_LENGTH;