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Regenerate verilog

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This commit is contained in:
Jessica Clarke
2020-07-13 18:54:53 +01:00
parent 26a5376f9c
commit e89f7a8130
294 changed files with 181908 additions and 323568 deletions
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343
src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v
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@@ -1,13 +1,13 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Fri Jul 10 20:55:21 BST 2020
// On Mon Jul 13 18:28:48 BST 2020
//
//
// Ports:
// Name I/O size props
// RDY_write_enq O 1 const
// read_deq O 434
// read_deq O 370
// RDY_read_deq O 1 const
// RDY_setLSQAtCommitNotified O 1 const
// RDY_setExecuted_deqLSQ O 1 const
@@ -26,14 +26,12 @@
// RDY_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// write_enq_x I 434
// write_enq_x I 370
// setExecuted_deqLSQ_cause I 14
// setExecuted_deqLSQ_ld_killed I 3
// setExecuted_doFinishAlu_0_set_csrData I 130
// setExecuted_doFinishAlu_0_set_cf I 329
// setExecuted_doFinishAlu_0_set_csrData I 131
// setExecuted_doFinishAlu_0_set_cause I 12
// setExecuted_doFinishAlu_1_set_csrData I 130
// setExecuted_doFinishAlu_1_set_cf I 329
// setExecuted_doFinishAlu_1_set_csrData I 131
// setExecuted_doFinishAlu_1_set_cause I 12
// setExecuted_doFinishFpuMulDiv_0_set_fflags I 5
// setExecuted_doFinishFpuMulDiv_0_set_cause I 6
@@ -90,13 +88,11 @@ module mkRobRowSynth(CLK,
RDY_setExecuted_deqLSQ,
setExecuted_doFinishAlu_0_set_csrData,
setExecuted_doFinishAlu_0_set_cf,
setExecuted_doFinishAlu_0_set_cause,
EN_setExecuted_doFinishAlu_0_set,
RDY_setExecuted_doFinishAlu_0_set,
setExecuted_doFinishAlu_1_set_csrData,
setExecuted_doFinishAlu_1_set_cf,
setExecuted_doFinishAlu_1_set_cause,
EN_setExecuted_doFinishAlu_1_set,
RDY_setExecuted_doFinishAlu_1_set,
@@ -134,12 +130,12 @@ module mkRobRowSynth(CLK,
input RST_N;
// action method write_enq
input [433 : 0] write_enq_x;
input [369 : 0] write_enq_x;
input EN_write_enq;
output RDY_write_enq;
// value method read_deq
output [433 : 0] read_deq;
output [369 : 0] read_deq;
output RDY_read_deq;
// action method setLSQAtCommitNotified
@@ -153,15 +149,13 @@ module mkRobRowSynth(CLK,
output RDY_setExecuted_deqLSQ;
// action method setExecuted_doFinishAlu_0_set
input [129 : 0] setExecuted_doFinishAlu_0_set_csrData;
input [328 : 0] setExecuted_doFinishAlu_0_set_cf;
input [130 : 0] setExecuted_doFinishAlu_0_set_csrData;
input [11 : 0] setExecuted_doFinishAlu_0_set_cause;
input EN_setExecuted_doFinishAlu_0_set;
output RDY_setExecuted_doFinishAlu_0_set;
// action method setExecuted_doFinishAlu_1_set
input [129 : 0] setExecuted_doFinishAlu_1_set_csrData;
input [328 : 0] setExecuted_doFinishAlu_1_set_cf;
input [130 : 0] setExecuted_doFinishAlu_1_set_csrData;
input [11 : 0] setExecuted_doFinishAlu_1_set_cause;
input EN_setExecuted_doFinishAlu_1_set;
output RDY_setExecuted_doFinishAlu_1_set;
@@ -204,7 +198,7 @@ module mkRobRowSynth(CLK,
output RDY_correctSpeculation;
// signals for module outputs
wire [433 : 0] read_deq;
wire [369 : 0] read_deq;
wire [128 : 0] getOrigPC, getOrigPredPC;
wire [31 : 0] getOrig_Inst;
wire RDY_correctSpeculation,
@@ -320,11 +314,6 @@ module mkRobRowSynth(CLK,
wire [13 : 0] m_trap_rl$D_IN;
wire m_trap_rl$EN;
// register m_tval_rl
reg [63 : 0] m_tval_rl;
wire [63 : 0] m_tval_rl$D_IN;
wire m_tval_rl$EN;
// register m_will_dirty_fpu_state
reg m_will_dirty_fpu_state;
wire m_will_dirty_fpu_state$D_IN, m_will_dirty_fpu_state$EN;
@@ -341,7 +330,6 @@ module mkRobRowSynth(CLK,
CAN_FIRE_RL_m_setPcWires,
CAN_FIRE_RL_m_spec_bits_canon,
CAN_FIRE_RL_m_trap_canon,
CAN_FIRE_RL_m_tval_canon,
CAN_FIRE_correctSpeculation,
CAN_FIRE_setExecuted_deqLSQ,
CAN_FIRE_setExecuted_doFinishAlu_0_set,
@@ -361,7 +349,6 @@ module mkRobRowSynth(CLK,
WILL_FIRE_RL_m_setPcWires,
WILL_FIRE_RL_m_spec_bits_canon,
WILL_FIRE_RL_m_trap_canon,
WILL_FIRE_RL_m_tval_canon,
WILL_FIRE_correctSpeculation,
WILL_FIRE_setExecuted_deqLSQ,
WILL_FIRE_setExecuted_doFinishAlu_0_set,
@@ -379,9 +366,9 @@ module mkRobRowSynth(CLK,
// remaining internal signals
reg [12 : 0] CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7,
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11,
CASE_write_enq_x_BITS_239_TO_238_0_0_CONCAT_wr_ETC__q18;
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18;
reg [11 : 0] CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
CASE_write_enq_x_BITS_253_TO_242_1_write_enq_x_ETC__q20;
CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22;
reg [4 : 0] CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2,
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5,
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6,
@@ -390,23 +377,23 @@ module mkRobRowSynth(CLK,
CASE_setExecuted_doFinishAlu_0_set_cause_BITS__ETC__q13,
CASE_setExecuted_doFinishAlu_1_set_cause_BITS__ETC__q14,
CASE_setExecuted_doFinishFpuMulDiv_0_set_cause_ETC__q12,
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q16,
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q17,
CASE_write_enq_x_BITS_259_TO_255_0_write_enq_x_ETC__q21;
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16,
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17,
CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23;
reg [3 : 0] CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4,
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8,
CASE_write_enq_x_BITS_230_TO_227_0_write_enq_x_ETC__q15;
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15;
reg [1 : 0] CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q19;
wire [260 : 0] m_scr_43_BIT_5_44_CONCAT_IF_m_scr_43_BIT_5_44__ETC___d1133;
wire [226 : 0] m_tval_rl_58_CONCAT_IF_m_ppc_vaddr_csrData_rl__ETC___d1131;
wire [128 : 0] IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d604,
IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d606;
wire [25 : 0] IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254,
IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341;
CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19,
CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20,
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21;
wire [196 : 0] m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115;
wire [162 : 0] IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113;
wire [128 : 0] IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588,
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590;
wire [12 : 0] IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d544,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d545;
wire [11 : 0] sb__h20471, upd__h10822;
wire [11 : 0] sb__h18415, upd__h9919;
wire [5 : 0] IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d71,
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d73;
wire [4 : 0] IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d336,
@@ -430,14 +417,14 @@ module mkRobRowSynth(CLK,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d537,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d539,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d541;
wire [1 : 0] IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d653;
wire IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d643,
IF_m_memAccessAtCommit_lat_1_whas__58_THEN_m_m_ETC___d664,
IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d584,
IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d593,
IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d586,
IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d595,
IF_m_rob_inst_state_lat_3_whas__19_THEN_m_rob__ETC___d631,
wire [1 : 0] IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637;
wire IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627,
IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648,
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568,
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577,
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570,
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579,
IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615,
IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42,
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d110,
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d121,
@@ -517,7 +504,7 @@ module mkRobRowSynth(CLK,
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d531,
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d62,
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d90,
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1409;
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345;
// action method write_enq
assign RDY_write_enq = 1'd1 ;
@@ -530,7 +517,7 @@ module mkRobRowSynth(CLK,
m_orig_inst,
m_iType,
m_rg_dst_reg,
m_scr_43_BIT_5_44_CONCAT_IF_m_scr_43_BIT_5_44__ETC___d1133 } ;
m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115 } ;
assign RDY_read_deq = 1'd1 ;
// action method setLSQAtCommitNotified
@@ -602,10 +589,6 @@ module mkRobRowSynth(CLK,
assign CAN_FIRE_RL_m_trap_canon = 1'd1 ;
assign WILL_FIRE_RL_m_trap_canon = 1'd1 ;
// rule RL_m_tval_canon
assign CAN_FIRE_RL_m_tval_canon = 1'd1 ;
assign WILL_FIRE_RL_m_tval_canon = 1'd1 ;
// rule RL_m_ppc_vaddr_csrData_canon
assign CAN_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
assign WILL_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
@@ -672,57 +655,33 @@ module mkRobRowSynth(CLK,
assign m_trap_lat_2$whas =
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[13] ||
EN_setExecuted_doFinishFpuMulDiv_0_set &&
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1409 ;
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345 ;
assign m_trap_lat_3$wget =
{ write_enq_x[240],
CASE_write_enq_x_BITS_239_TO_238_0_0_CONCAT_wr_ETC__q18 } ;
{ write_enq_x[176],
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 } ;
assign m_ppc_vaddr_csrData_lat_0$wget =
setExecuted_doFinishAlu_0_set_csrData[129] ?
{ 2'd2, setExecuted_doFinishAlu_0_set_csrData[128:0] } :
{ 2'd0,
setExecuted_doFinishAlu_0_set_cf[165],
setExecuted_doFinishAlu_0_set_cf[84:69],
setExecuted_doFinishAlu_0_set_cf[67:66],
setExecuted_doFinishAlu_0_set_cf[68],
~setExecuted_doFinishAlu_0_set_cf[65:47],
IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254[25:17],
~IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254[16:15],
IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254[14:3],
~IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254[2],
IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254[1:0],
setExecuted_doFinishAlu_0_set_cf[162:99] } ;
{ CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19,
setExecuted_doFinishAlu_0_set_csrData[128:0] } ;
assign m_ppc_vaddr_csrData_lat_1$wget =
setExecuted_doFinishAlu_1_set_csrData[129] ?
{ 2'd2, setExecuted_doFinishAlu_1_set_csrData[128:0] } :
{ 2'd0,
setExecuted_doFinishAlu_1_set_cf[165],
setExecuted_doFinishAlu_1_set_cf[84:69],
setExecuted_doFinishAlu_1_set_cf[67:66],
setExecuted_doFinishAlu_1_set_cf[68],
~setExecuted_doFinishAlu_1_set_cf[65:47],
IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341[25:17],
~IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341[16:15],
IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341[14:3],
~IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341[2],
IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341[1:0],
setExecuted_doFinishAlu_1_set_cf[162:99] } ;
{ CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20,
setExecuted_doFinishAlu_1_set_csrData[128:0] } ;
assign m_ppc_vaddr_csrData_lat_2$wget =
{ 2'd1, setExecuted_doFinishMem_vaddr } ;
assign m_ppc_vaddr_csrData_lat_3$wget =
{ CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q19,
{ CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21,
write_enq_x[160:32] } ;
assign m_rob_inst_state_lat_4$whas =
EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done ;
// register m_claimed_phy_reg
assign m_claimed_phy_reg$D_IN = write_enq_x[241] ;
assign m_claimed_phy_reg$D_IN = write_enq_x[177] ;
assign m_claimed_phy_reg$EN = EN_write_enq ;
// register m_csr
assign m_csr$D_IN =
{ write_enq_x[254],
CASE_write_enq_x_BITS_253_TO_242_1_write_enq_x_ETC__q20 } ;
{ write_enq_x[190],
CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 } ;
assign m_csr$EN = EN_write_enq ;
// register m_epochIncremented
@@ -739,13 +698,13 @@ module mkRobRowSynth(CLK,
assign m_fflags_rl$EN = 1'd1 ;
// register m_iType
assign m_iType$D_IN = write_enq_x[272:268] ;
assign m_iType$D_IN = write_enq_x[208:204] ;
assign m_iType$EN = EN_write_enq ;
// register m_ldKilled_rl
assign m_ldKilled_rl$D_IN =
{ IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d643,
IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d653 } ;
{ IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627,
IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637 } ;
assign m_ldKilled_rl$EN = 1'd1 ;
// register m_lsqAtCommitNotified_rl
@@ -760,7 +719,7 @@ module mkRobRowSynth(CLK,
// register m_memAccessAtCommit_rl
assign m_memAccessAtCommit_rl$D_IN =
IF_m_memAccessAtCommit_lat_1_whas__58_THEN_m_m_ETC___d664 ;
IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648 ;
assign m_memAccessAtCommit_rl$EN = 1'd1 ;
// register m_nonMMIOStDone_rl
@@ -772,25 +731,25 @@ module mkRobRowSynth(CLK,
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
// register m_orig_inst
assign m_orig_inst$D_IN = write_enq_x[304:273] ;
assign m_orig_inst$D_IN = write_enq_x[240:209] ;
assign m_orig_inst$EN = EN_write_enq ;
// register m_pc_rl
assign m_pc_rl$D_IN = EN_write_enq ? write_enq_x[433:305] : m_pc_rl ;
assign m_pc_rl$D_IN = EN_write_enq ? write_enq_x[369:241] : m_pc_rl ;
assign m_pc_rl$EN = 1'd1 ;
// register m_ppc_vaddr_csrData_rl
assign m_ppc_vaddr_csrData_rl$D_IN =
{ IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d586 ?
{ IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570 ?
2'd0 :
(IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d595 ?
(IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579 ?
2'd1 :
2'd2),
IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d606 } ;
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590 } ;
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
// register m_rg_dst_reg
assign m_rg_dst_reg$D_IN = write_enq_x[267:261] ;
assign m_rg_dst_reg$D_IN = write_enq_x[203:197] ;
assign m_rg_dst_reg$EN = EN_write_enq ;
// register m_rob_inst_state_rl
@@ -798,18 +757,18 @@ module mkRobRowSynth(CLK,
EN_write_enq ?
write_enq_x[25] :
m_rob_inst_state_lat_4$whas ||
IF_m_rob_inst_state_lat_3_whas__19_THEN_m_rob__ETC___d631 ;
IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615 ;
assign m_rob_inst_state_rl$EN = 1'd1 ;
// register m_scr
assign m_scr$D_IN =
{ write_enq_x[260],
CASE_write_enq_x_BITS_259_TO_255_0_write_enq_x_ETC__q21 } ;
{ write_enq_x[196],
CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 } ;
assign m_scr$EN = EN_write_enq ;
// register m_spec_bits_rl
assign m_spec_bits_rl$D_IN =
EN_correctSpeculation ? upd__h10822 : sb__h20471 ;
EN_correctSpeculation ? upd__h9919 : sb__h18415 ;
assign m_spec_bits_rl$EN = 1'd1 ;
// register m_trap_rl
@@ -818,10 +777,6 @@ module mkRobRowSynth(CLK,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d545 } ;
assign m_trap_rl$EN = 1'd1 ;
// register m_tval_rl
assign m_tval_rl$D_IN = EN_write_enq ? write_enq_x[226:163] : m_tval_rl ;
assign m_tval_rl$EN = 1'd1 ;
// register m_will_dirty_fpu_state
assign m_will_dirty_fpu_state$D_IN = write_enq_x[26] ;
assign m_will_dirty_fpu_state$EN = EN_write_enq ;
@@ -975,60 +930,73 @@ module mkRobRowSynth(CLK,
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d73,
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d356 } :
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d544 ;
assign IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d643 =
assign IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627 =
!EN_write_enq &&
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[2] :
m_ldKilled_rl[2]) ;
assign IF_m_ldKilled_lat_1_whas__34_THEN_m_ldKilled_l_ETC___d653 =
assign IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637 =
EN_write_enq ?
2'b10 :
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[1:0] :
m_ldKilled_rl[1:0]) ;
assign IF_m_memAccessAtCommit_lat_1_whas__58_THEN_m_m_ETC___d664 =
assign IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648 =
EN_write_enq ?
write_enq_x[272:268] == 5'd19 :
write_enq_x[208:204] == 5'd19 :
(EN_setExecuted_doFinishMem ?
setExecuted_doFinishMem_access_at_commit :
m_memAccessAtCommit_rl) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d584 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd0 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd0 :
m_ppc_vaddr_csrData_rl[130:129] == 2'd0) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d593 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd1 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd1 :
m_ppc_vaddr_csrData_rl[130:129] == 2'd1) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d604 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[128:0] :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[128:0] :
m_ppc_vaddr_csrData_rl[128:0]) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d586 =
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd0 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd0 :
IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d584) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d595 =
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd1 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd1 :
IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d593) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__64_THEN_m_p_ETC___d606 =
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[128:0] :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[128:0] :
IF_m_ppc_vaddr_csrData_lat_1_whas__72_THEN_m_p_ETC___d604) ;
assign IF_m_rob_inst_state_lat_3_whas__19_THEN_m_rob__ETC___d631 =
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588) ;
assign IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113 =
{ CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
m_ppc_vaddr_csrData_rl[128:0],
m_fflags_rl,
m_will_dirty_fpu_state,
m_rob_inst_state_rl,
m_lsqTag,
m_ldKilled_rl,
m_memAccessAtCommit_rl,
m_lsqAtCommitNotified_rl,
m_nonMMIOStDone_rl,
m_epochIncremented,
m_spec_bits_rl } ;
assign IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615 =
EN_setExecuted_deqLSQ ||
EN_setExecuted_doFinishFpuMulDiv_0_set ||
EN_setExecuted_doFinishAlu_1_set ||
@@ -1514,21 +1482,7 @@ module mkRobRowSynth(CLK,
(m_trap_lat_2$whas ?
m_trap_lat_2$wget[4:0] == 5'd0 :
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d88) ;
assign IF_setExecuted_doFinishAlu_0_set_cf_BIT_47_246_ETC___d1254 =
setExecuted_doFinishAlu_0_set_cf[47] ?
{ setExecuted_doFinishAlu_0_set_cf[38:30],
setExecuted_doFinishAlu_0_set_cf[46:44],
setExecuted_doFinishAlu_0_set_cf[26:16],
setExecuted_doFinishAlu_0_set_cf[43:41] } :
setExecuted_doFinishAlu_0_set_cf[38:13] ;
assign IF_setExecuted_doFinishAlu_1_set_cf_BIT_47_333_ETC___d1341 =
setExecuted_doFinishAlu_1_set_cf[47] ?
{ setExecuted_doFinishAlu_1_set_cf[38:30],
setExecuted_doFinishAlu_1_set_cf[46:44],
setExecuted_doFinishAlu_1_set_cf[26:16],
setExecuted_doFinishAlu_1_set_cf[43:41] } :
setExecuted_doFinishAlu_1_set_cf[38:13] ;
assign m_scr_43_BIT_5_44_CONCAT_IF_m_scr_43_BIT_5_44__ETC___d1133 =
assign m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115 =
{ m_scr[5],
CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2,
m_csr[12],
@@ -1536,28 +1490,14 @@ module mkRobRowSynth(CLK,
m_claimed_phy_reg,
m_trap_rl[13],
CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7,
m_tval_rl_58_CONCAT_IF_m_ppc_vaddr_csrData_rl__ETC___d1131 } ;
assign m_tval_rl_58_CONCAT_IF_m_ppc_vaddr_csrData_rl__ETC___d1131 =
{ m_tval_rl,
CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
m_ppc_vaddr_csrData_rl[128:0],
m_fflags_rl,
m_will_dirty_fpu_state,
m_rob_inst_state_rl,
m_lsqTag,
m_ldKilled_rl,
m_memAccessAtCommit_rl,
m_lsqAtCommitNotified_rl,
m_nonMMIOStDone_rl,
m_epochIncremented,
m_spec_bits_rl } ;
assign sb__h20471 = EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
assign setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1409 =
IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113 } ;
assign sb__h18415 = EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
assign setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345 =
setExecuted_doFinishFpuMulDiv_0_set_cause[5] &&
(m_trap_lat_1$whas ?
!m_trap_lat_1$wget[13] :
IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42) ;
assign upd__h10822 = sb__h20471 & correctSpeculation_mask ;
assign upd__h9919 = sb__h18415 & correctSpeculation_mask ;
always@(m_ppc_vaddr_csrData_rl)
begin
case (m_ppc_vaddr_csrData_rl[130:129])
@@ -1886,17 +1826,17 @@ module mkRobRowSynth(CLK,
end
always@(write_enq_x)
begin
case (write_enq_x[230:227])
case (write_enq_x[166:163])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_write_enq_x_BITS_230_TO_227_0_write_enq_x_ETC__q15 =
write_enq_x[230:227];
default: CASE_write_enq_x_BITS_230_TO_227_0_write_enq_x_ETC__q15 =
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 =
write_enq_x[166:163];
default: CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 =
4'd15;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[231:227])
case (write_enq_x[167:163])
5'd0,
5'd1,
5'd2,
@@ -1920,15 +1860,15 @@ module mkRobRowSynth(CLK,
5'd24,
5'd25,
5'd26:
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q16 =
write_enq_x[231:227];
default: CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q16 =
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 =
write_enq_x[167:163];
default: CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 =
5'd27;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[231:227])
case (write_enq_x[167:163])
5'd0,
5'd1,
5'd2,
@@ -1943,45 +1883,63 @@ module mkRobRowSynth(CLK,
5'd12,
5'd13,
5'd15:
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q17 =
write_enq_x[231:227];
default: CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q17 =
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 =
write_enq_x[167:163];
default: CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 =
5'd28;
endcase
end
always@(write_enq_x or
CASE_write_enq_x_BITS_230_TO_227_0_write_enq_x_ETC__q15 or
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q16 or
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q17)
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 or
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 or
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17)
begin
case (write_enq_x[239:238])
case (write_enq_x[175:174])
2'd0:
CASE_write_enq_x_BITS_239_TO_238_0_0_CONCAT_wr_ETC__q18 =
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
{ 2'd0,
write_enq_x[237:232],
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q16 };
write_enq_x[173:168],
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 };
2'd1:
CASE_write_enq_x_BITS_239_TO_238_0_0_CONCAT_wr_ETC__q18 =
{ write_enq_x[239:238],
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
{ write_enq_x[175:174],
6'h2A,
CASE_write_enq_x_BITS_231_TO_227_0_write_enq_x_ETC__q17 };
default: CASE_write_enq_x_BITS_239_TO_238_0_0_CONCAT_wr_ETC__q18 =
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 };
default: CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
{ 9'd298,
CASE_write_enq_x_BITS_230_TO_227_0_write_enq_x_ETC__q15 };
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 };
endcase
end
always@(setExecuted_doFinishAlu_0_set_csrData)
begin
case (setExecuted_doFinishAlu_0_set_csrData[130:129])
2'd0, 2'd1:
CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19 =
setExecuted_doFinishAlu_0_set_csrData[130:129];
default: CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19 = 2'd2;
endcase
end
always@(setExecuted_doFinishAlu_1_set_csrData)
begin
case (setExecuted_doFinishAlu_1_set_csrData[130:129])
2'd0, 2'd1:
CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20 =
setExecuted_doFinishAlu_1_set_csrData[130:129];
default: CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20 = 2'd2;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[162:161])
2'd0, 2'd1:
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q19 =
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21 =
write_enq_x[162:161];
default: CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q19 = 2'd2;
default: CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21 = 2'd2;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[253:242])
case (write_enq_x[189:178])
12'd1,
12'd2,
12'd3,
@@ -2028,19 +1986,19 @@ module mkRobRowSynth(CLK,
12'd3858,
12'd3859,
12'd3860:
CASE_write_enq_x_BITS_253_TO_242_1_write_enq_x_ETC__q20 =
write_enq_x[253:242];
default: CASE_write_enq_x_BITS_253_TO_242_1_write_enq_x_ETC__q20 =
CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 =
write_enq_x[189:178];
default: CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 =
12'd2303;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[259:255])
case (write_enq_x[195:191])
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
CASE_write_enq_x_BITS_259_TO_255_0_write_enq_x_ETC__q21 =
write_enq_x[259:255];
default: CASE_write_enq_x_BITS_259_TO_255_0_write_enq_x_ETC__q21 =
CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 =
write_enq_x[195:191];
default: CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 =
5'd10;
endcase
end
@@ -2063,7 +2021,6 @@ module mkRobRowSynth(CLK,
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
m_trap_rl <= `BSV_ASSIGNMENT_DELAY 14'h2AAA;
m_tval_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
end
else
begin
@@ -2089,7 +2046,6 @@ module mkRobRowSynth(CLK,
if (m_spec_bits_rl$EN)
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_rl$D_IN;
if (m_trap_rl$EN) m_trap_rl <= `BSV_ASSIGNMENT_DELAY m_trap_rl$D_IN;
if (m_tval_rl$EN) m_tval_rl <= `BSV_ASSIGNMENT_DELAY m_tval_rl$D_IN;
end
if (m_claimed_phy_reg$EN)
m_claimed_phy_reg <= `BSV_ASSIGNMENT_DELAY m_claimed_phy_reg$D_IN;
@@ -2130,7 +2086,6 @@ module mkRobRowSynth(CLK,
m_scr = 6'h2A;
m_spec_bits_rl = 12'hAAA;
m_trap_rl = 14'h2AAA;
m_tval_rl = 64'hAAAAAAAAAAAAAAAA;
m_will_dirty_fpu_state = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
@@ -2144,13 +2099,17 @@ module mkRobRowSynth(CLK,
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
(m_csr[12] || m_scr[5]) !=
setExecuted_doFinishAlu_0_set_csrData[129])
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd0 &&
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd1 &&
!m_csr[12] &&
!m_scr[5])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
(m_csr[12] || m_scr[5]) !=
setExecuted_doFinishAlu_1_set_csrData[129])
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd0 &&
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd1 &&
!m_csr[12] &&
!m_scr[5])
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&