Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0
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@@ -288,7 +288,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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// To avoid posting timer interrupt repeatedly, we keep a copy of MTIP
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// here. Since each core cannot write MTIP by CSRXXX inst, the only way to
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// change MTIP is through here.
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Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(False));
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// We initialize to True to avoid an timer interrupt at start of time.
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Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(True));
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// pass mtime to each core
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rule propagateTime(state != Init);
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@@ -321,18 +322,15 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
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// check for timer interrupt
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Vector#(CoreNum, Bool) needTimerInt = replicate(False);
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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if(!mtip[i]
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&& (mtimecmp[i] <= mtime)
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&& (mtimecmp [i] != 0)) // Avoid interrupt until mtimecmp has actually been written
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begin
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cores[i].pRq.enq(MMIOPRq {
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target: MTIP,
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func: St,
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data: 1
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});
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mtip[i] <= True;
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needTimerInt[i] = True;
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end
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if(!mtip[i] && mtimecmp[i] <= mtime) begin
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cores[i].pRq.enq(MMIOPRq {
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target: MTIP,
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func: St,
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data: 1
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});
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mtip[i] <= True;
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needTimerInt[i] = True;
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end
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end
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if(needTimerInt != replicate(False)) begin
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state <= WaitResp;
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@@ -531,7 +531,10 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
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&&& ((dInst.iType == Csr)
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&& ((csr == CSRfflags) || (csr == CSRfrm) || (csr == CSRfcsr))))
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begin
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will_dirty_fpu_state = True;
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Bool is_CSRR_W = (dInst.execFunc == tagged Alu Csrw);
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Bool rs1_is_0 = ((arch_regs.src2 == tagged Valid (tagged Gpr 0))
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|| (dInst.imm == tagged Valid 0));
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will_dirty_fpu_state = (is_CSRR_W || (! rs1_is_0));
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end
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RobInstState rob_inst_state = to_exec ? NotDone : Executed;
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