Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0

This commit is contained in:
rsnikhil
2020-03-11 22:42:18 -04:00
parent a19eb97f34
commit f02e9af515
19 changed files with 10931 additions and 10950 deletions

View File

@@ -288,7 +288,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// To avoid posting timer interrupt repeatedly, we keep a copy of MTIP
// here. Since each core cannot write MTIP by CSRXXX inst, the only way to
// change MTIP is through here.
Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(False));
// We initialize to True to avoid an timer interrupt at start of time.
Vector#(CoreNum, Reg#(Bool)) mtip <- replicateM(mkReg(True));
// pass mtime to each core
rule propagateTime(state != Init);
@@ -321,18 +322,15 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// check for timer interrupt
Vector#(CoreNum, Bool) needTimerInt = replicate(False);
for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
if(!mtip[i]
&& (mtimecmp[i] <= mtime)
&& (mtimecmp [i] != 0)) // Avoid interrupt until mtimecmp has actually been written
begin
cores[i].pRq.enq(MMIOPRq {
target: MTIP,
func: St,
data: 1
});
mtip[i] <= True;
needTimerInt[i] = True;
end
if(!mtip[i] && mtimecmp[i] <= mtime) begin
cores[i].pRq.enq(MMIOPRq {
target: MTIP,
func: St,
data: 1
});
mtip[i] <= True;
needTimerInt[i] = True;
end
end
if(needTimerInt != replicate(False)) begin
state <= WaitResp;

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@@ -531,7 +531,10 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
&&& ((dInst.iType == Csr)
&& ((csr == CSRfflags) || (csr == CSRfrm) || (csr == CSRfcsr))))
begin
will_dirty_fpu_state = True;
Bool is_CSRR_W = (dInst.execFunc == tagged Alu Csrw);
Bool rs1_is_0 = ((arch_regs.src2 == tagged Valid (tagged Gpr 0))
|| (dInst.imm == tagged Valid 0));
will_dirty_fpu_state = (is_CSRR_W || (! rs1_is_0));
end
RobInstState rob_inst_state = to_exec ? NotDone : Executed;