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Bug fixes; now passing rv64mi-p-csr ISA test

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Modified:
    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Bug fixes in 'getTrap' function:
	- Trap if Fpu regs are accessed but mstatus_fs is "Off" (2'b00)
	- Trap if r/w or privilege denies access to CSR in CSRRW/C/S instruction
    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Bug fix: add support for 'u' bit in function 'getExtensionBits'
This commit is contained in:
rsnikhil
2019-04-10 23:06:27 -04:00
parent f369ed14e3
commit f280287589
22 changed files with 26993 additions and 26725 deletions
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src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -108,6 +108,7 @@ function Bit#(2) getXLBits = 2'b10; // MXL/SXL/UXL fix to RV64
function Bit#(26) getExtensionBits(RiscVISASubset isa);
// include S and I by default
Bit#(26) ext = 26'b00000001000000000100000000;
if (isa.u) ext = ext | 26'b00000100000000000000000000;
if (isa.m) ext = ext | 26'b00000000000001000000000000;
if (isa.a) ext = ext | 26'b00000000000000000000000001;
if (isa.f) ext = ext | 26'b00000000000000000000100000;