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Added missing ifdefs

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This commit is contained in:
Franz Fuchs
2021-06-24 08:35:21 +01:00
parent 0c80ac30bb
commit f83d7b1554
3 changed files with 21 additions and 7 deletions
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9
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -196,10 +196,12 @@ interface AluExeInput;
// performance
method Bool doStats;
`ifdef PERFORMANCE_MONITORING
// check previous branch targets
method Bool checkTarget(CapMem ppc);
// check (previous) return targets
method Bool checkReturnTarget(CapMem ppc);
`endif
endinterface
interface AluExePipeline;
@@ -296,9 +298,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
let ppc = inIfc.rob_getPredPC(x.tag);
let orig_inst = inIfc.rob_getOrig_Inst (x.tag);
// TODO: split into Br, jumps, and rets
`ifdef PERFORMANCE_MONITORING
let ppc_addr = getAddr(ppc);
let pc_addr = getAddr(pc);
EventsTransExe events = unpack(0);
@@ -323,10 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
events.evt_WILD_JUMP = 1;
events_reg <= events;
end
end
end
`endif
// go to next stage

12
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -132,10 +132,12 @@ interface CommitInput;
// deadlock check
method Bool checkDeadlock;
`ifdef PERFORMANCE_MONITORING
// update branch targets
method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
// update return targets
method Action updateReturnTargets(Vector#(SupSize, Maybe#(CapMem)) returnTargets);
`endif
`ifdef INCLUDE_TANDEM_VERIF
interface Vector #(SupSize, Put #(Trace_Data2)) v_to_TV;
@@ -1093,14 +1095,18 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Data po_mstatus = ?;
`endif
`ifdef PERFORMANCE_MONITORING
// update targets vector
Vector#(SupSize, Maybe#(CapMem)) targets;
// update return targets vector
Vector#(SupSize, Maybe#(CapMem)) returnTargets;
`endif
// compute what actions to take
for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
`ifdef PERFORMANCE_MONITORING
Maybe#(CapMem) tar = tagged Invalid;
Maybe#(CapMem) retTar = tagged Invalid;
`endif
if(!stop && rob.deqPort[i].canDeq) begin
let x = rob.deqPort[i].deq_data;
let inst_tag = rob.deqPort[i].getDeqInstTag;
@@ -1144,6 +1150,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
// inst can be committed, deq it
rob.deqPort[i].deq;
`ifdef PERFORMANCE_MONITORING
// return address stack link reg is x1 or x5
function Bool linkedR(Maybe#(ArchRIndx) register);
Bool res = False;
@@ -1172,6 +1179,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
tar = tagged Valid x.ppc_vaddr_csrData.PPC;
$display("BRANCH target added: pc = ", fshow(x.pc), " ppc = ", fshow(tar));
end*/
`endif
// every inst here should have been renamed, commit renaming
regRenamingTable.commit[i].commit;
@@ -1248,8 +1256,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (opcode == opcMiscMem && funct3 == fnFENCE) fenceCnt = fenceCnt + 1;
end
end
`ifdef PERFORMANCE_MONITORING
targets[i] = tar;
returnTargets[i] = retTar;
`endif
end
rg_serial_num <= rg_serial_num + instret;
@@ -1312,10 +1322,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
events.evt_FP = fpuCnt;
events.evt_FENCE = fenceCnt;
events_reg <= events;
`endif
inIfc.updateTargets(targets);
inIfc.updateReturnTargets(returnTargets);
`endif
`ifdef RVFI
rvfiQ.enq(rvfis);