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Adapt the PLIC instantiation and wiring to support multiple cores

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This commit is contained in:
Jessica Clarke
2020-10-16 16:14:24 +01:00
committed by Peter Rugg
parent cedb4c279d
commit fb5339e9ca
7 changed files with 36 additions and 25 deletions
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22
src_Core/Core/CoreW.bsv
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@@ -37,7 +37,7 @@ package CoreW;
//
// mkCoreW instantiates:
// - mkProc (the RISC-V CPU, a version of MIT's RISCY-OOO)
// - mkPLIC_16_2_7
// - mkPLIC_16_CoreNumX2_7
// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
// and connects them all up.
@@ -81,11 +81,12 @@ import Debug_Module :: *;
`endif
import CoreW_IFC :: *;
import PLIC :: *;
import PLIC_16_2_7 :: *;
import Proc_IFC :: *;
import Proc :: *;
import PLIC :: *;
import PLIC_16_CoreNumX2_7 :: *;
`ifdef INCLUDE_TANDEM_VERIF
import TV_Info :: *;
import Trace_Data2 :: *;
@@ -190,7 +191,7 @@ module mkCoreW #(Reset dm_power_on_reset)
`endif
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;
PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7;
`ifdef INCLUDE_GDB_CONTROL
// Debug Module
@@ -402,13 +403,16 @@ module mkCoreW #(Reset dm_power_on_reset)
// Connect external interrupt lines from PLIC to CPU
rule rl_relay_external_interrupts; // from PLIC
Bool meip = plic.v_targets [0].m_eip;
proc.m_external_interrupt_req (meip);
Vector #(CoreNum, Bool) meips;
Vector #(CoreNum, Bool) seips;
Bool seip = plic.v_targets [1].m_eip;
proc.s_external_interrupt_req (seip);
for (Integer i = 0; i < valueof(CoreNum); i = i + 1) begin
meips [i] = plic.v_targets [2 * i].m_eip;
seips [i] = plic.v_targets [2 * i + 1].m_eip;
end
// $display ("%0d: Core.rl_relay_external_interrupts: relaying: %d", cur_cycle, pack (x));
proc.m_external_interrupt_req (meips);
proc.s_external_interrupt_req (seips);
endrule
// ================================================================

2
src_Core/Core/CoreW_IFC.bsv
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@@ -25,7 +25,7 @@ package CoreW_IFC;
// interface and its module is called 'CoreW', to disambiguate.
// - mkFabric_2x3
// - mkNear_Mem_IO_AXI4
// - mkPLIC_16_2_7
// - mkPLIC_16_CoreNumX2_7
// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)