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Adapt the PLIC instantiation and wiring to support multiple cores

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This commit is contained in:
Jessica Clarke
2020-10-16 16:14:24 +01:00
committed by Peter Rugg
parent cedb4c279d
commit fb5339e9ca
7 changed files with 36 additions and 25 deletions
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src_SSITH_P3/xilinx_ip/component.xml
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@@ -2532,7 +2532,7 @@
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/mkPLIC_16_2_7.v</spirit:name>
<spirit:name>hdl/mkPLIC_16_CoreNumX2_7.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
@@ -3159,7 +3159,7 @@
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/mkPLIC_16_2_7.v</spirit:name>
<spirit:name>hdl/mkPLIC_16_CoreNumX2_7.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>