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Merge branch 'master' of https://github.com/bluespec/Toooba

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rsnikhil
2019-04-17 18:09:20 -04:00
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LICENSE
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@@ -1,3 +1,18 @@
This repository contains code with two licenses.
1. See: src_Core/RISCY_OOO/LICENSE_RISCY-OOO
The code in src_Core/RISCY_OOO is mostly a copy of MIT's
'riscy-ooo' processor, free and open-source under
LICENSE_RISC-OOO.
That code has been slightly modified by Bluespec, Inc. (see README for details).
2. Bluespec's modifications in src_Core/RISCY_OOO and the rest of this
repository are licensed under the license shown below.
>================================================================
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/

240
README.md
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@@ -1,9 +1,5 @@
# Open-source RISC-V CPUs from Bluespec, Inc.
***** UNDER CONSTRUCTION *****
***** PLEASE COME BACK LATER (EARLY APRIL 2019) *****
This is one of a family of free, open-source RISC-V CPUs created by Bluespec, Inc.
- [Piccolo](https://github.com/bluespec/Piccolo): 3-stage, in-order pipeline
@@ -16,8 +12,13 @@ This is one of a family of free, open-source RISC-V CPUs created by Bluespec, In
64-bit operation, an MMU (Virtual Memory) and more performance than
Piccolo-class processors.
- [Tooba](https://github.com/bluespec/Tooba): superscalar, out-of-order
pipeline, slight variation on MIT's RISCY-OOO [In progress!]
- [Toooba](https://github.com/bluespec/Toooba): superscalar, out-of-order
pipeline, slight variation on MIT's RISCY-OOO
Toooba is intended as a high-end application processor.
The three repo structures are nearly identical, and the ways to build
and run are identical.
----------------------------------------------------------------
### Note re. distribution of MIT RISCY-OOO sources.
@@ -28,33 +29,206 @@ The directory `src_Core/RISCY_OOO` contains sources copied from MIT's
[Note: MIT's repository is on an MIT git server, which can only be
accessed with credentials; hence the local copy in of these files.]
----------------------------------------------------------------
### Building and running Tooba
Bluespec's modifications to files in src_Core/RISCY_OOO are relatively
small and mostly additive:
You will need:
- A Bluespec tools installation (so you can run 'bsc', the Bluespec
compiler for BSV). We recommend version 2018.10.beta1 or later.
- A Verilator installation. We recommend version 3.922 or later.
Then:
$ cd builds/RV64ADFIMSU_Tuba_verilator
$ make all
This will compile BSV sources using the 'bsc' compiler into Verilog in
the directory `Verilog_RTL`, then compile and link into a verilator
executable `exe_HW_sim`.
Then:
$ make test (1)
$ make TEST=<isa_test_name> test (2)
$ make isa_tests (3)
(1) Will run a single ISA test, `rv64ui-p-add`.
(2) Will do the same, but with the ISA test whose name you supply.
(3) Will run ISA tests for RV64G.
- To add the RISC-V 'C' extension (compressed instructions)
- To add support for Bluespec's Tandem Verification
- To add support for Bluespec's Debug Module.
- To fix about bugs leading to about half a dozen failures of standard RISC-V ISA tests
----------------------------------------------------------------
### About the source codes (in BSV and Verilog)
The BSV source code in this repository, from which the synthesizable
Verilog RTL in this repository is generated, is highly parameterized
to allow generating many possible configurations, some of which are
adequate to boot a Linux kernel.
The pre-generated synthesizable Verilog RTL source files in this
repository are for one specific configuration:
1. RV64ACDFIMSU (a.k.a. RV64GC)
- RV64I: base RV64 integer instructions
- 'A' extension: atomic memory ops
- 'C' extension: compressed instructions
- 'D' extension: double-precision floating point instructions
- 'F' extension: single-precision floating point instructions
- 'M' extension: integer multiply/divide instructions
- Privilege levels M (machine), S (Supervisor) and U (user)
- Supports external, timer, software and non-maskable interrupts
- Passes all riscv-isa tests for RV64ACDFIMSU
- Boots the Linux kernel
If you want to generate other Verilog variants, you'll need a Bluespec
`bsc` compiler [Note: Bluespec, Inc. provides free licenses to
academia and for non-profit research].
### Testbench included
This repository contains a simple testbench (a small SoC) with which
one can run RISC-V binaries in simulation by loading standard mem hex
files and executing in Bluespec's Bluesim, Verilator simulation or
iVerilog simulation. The testbench contains an AXI4 interconnect
fabric that connects the CPU to models of a boot ROM, a memory, a
timer and a UART for console I/O.
[Note: **iverilog functionality is currently limited** because we are
still working out robust mechanisms to import C code, which is used in
parts of the testbench.]
This repository contains one sample build directory, to build
an RV64ACDFIMSU simulator, using Verilator Verilog simulation.
The generated Verilog is synthesizable. Bluespec tests all this code
on Xilinx FPGAs.
#### Plans
- Ongoing continuous micro-architectural improvements for performance and hardware area.
----------------------------------------------------------------
## Source codes
This repository contains two levels of source code: Verilog and BSV.
**Verilog RTL** can be found in directories with names suffixed in
'_verilator' or '_iverilog' in the 'builds' directory:
builds/..._<verilator or iverilog>/Verilog_RTL/
[There is no difference between Verilog in a Verilator directory
vs. the corresponding iverilog directory. ]
The Verilog RTL is _synthesizable_ (and hence acceptable to
Verilator). It can be simulated in any Verilog simulator (we provide
Makefiles to build simulation executables for Verilator and for Icarus
Verilog (iverilog)).
The RTL represents RISC-V CPU RTL, plus a rudimentary surrounding SoC
enabling immediate simulation here, and which is rich enough to enable
booting a Linux kernel. Users are free to use the CPU RTL in their
own Verilog system designs. The top-level module for the CPU RTL is
`Verilog_RTL/mkProc.v`. The top-level module for the surrounding
SoC is `Verilog_RTL/mkTop_HW_Side.v`. The SoC has an AXI4
fabric, a timer, a software-interrupt device, and a UART. Additional
library RTL can be found in the directory `src_bsc_lib_RTL`.
**Bluespec BSV** source code (which was used to generate the Verilog RTL) can be found in:
- `src_Core/`, for the CPU core, with sub-directories:
- `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv)
- 'CPU/': more CPU core sources
- 'RISCY_OOO': the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
- `ISA/`: generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific)
- 'PLIC/': Platform-Level Interrupt Controller (standard RISC-V spec)
- `BSV_Additional_Libs/`: generic utilities (not CPU-specific)
- `Debug_Module/`: RISC-V Debug Module to debug the CPU from GDB or other debuggers
- `src_Testbench/`, for the surrounding testbench, with sub-directories:
- `Top/`: The system top-level (`Top_HW_Side.bsv`), a memory model
that loads from a memory hex file, and some imported C
functions for polled reads from the console tty (not currently
available for Icarus Verilog).
- `SoC/`: An interconnect, a boot ROM, a memory controller, a timer
and software-interrupt device, and a UART for console tty I/O.
- `Fabrics/`: Generic AXI4 code for the SoC fabric.
The BSV source code has a rich set of parameters. The provided RTL
source has been generated from the BSV source automatically using
Bluespec's `bsc` compiler, with certain particular sets of choices for
the various parameters. The generated RTL is not parameterized.
To generate Verilog variants with other parameter choices, the user
will need Bluespec's `bsc` compiler. See the next section for
examples of how the build is configured for different ISA features.
In fact the CPU also supports a "Tandem Verifier" that produces an
instruction-by-instruction trace that can be checked for correctness
against a RISC-V Golden Reference Model. Please contact Bluespec,
Inc. for more information.
----------------------------------------------------------------
### Building and running from the Verilog sources, out of the box
In the Verilog-build directory:
builds/RV64ACDFIMSU_Toooba_verilator/
- `$ make simulator` will create a Verilog simulation executable using Verilator
- `$ make test` will run the executable on the standard RISC-V ISA
test `rv32ui-p-add` or `rv64ui-p-add`, which is one of the
tests in the `Tests/isa/` directory. Examining the `test:`
target in `Makefile`, we see that it first runs the program
`Tests/elf_to_hex/elf_to_hex` on the `rv32ui-p-add` or
`rv64ui-p-add` ELF file to create a `Mem.hex` file, and then
runs the simulation executable which loads this `Mem.hex` file
into its memory.
- `$ make TEST=<isa_test_name> test` will run the executable on the
standard RISC-V ISA test whose name is supplied.
The full set of standard isa tests are in the `Tests/isa/` directory.
- `$ make isa_tests` will run the executable on
all the standard RISC-V ISA tests relevant for RV64ACDFIMSU (regression testing).
This uses the Python script `Tests/Run_regression.py`.
Please see the documentation at the top of that program for details.
#### Tool dependencies:
We test our builds with the following versions
Verilator. Later versions are probably ok; we have observed some
problems with earlier versions.
$ verilator --version
Verilator 3.922 2018-03-17 rev verilator_3_920-32-gdf3d1a4
----------------------------------------------------------------
### What you can build and run if you have Bluespec's `bsc` compiler
[Note: Bluespec, Inc. provides free licenses to academia and for non-profit research].
Note: even without Bluespec's `bsc` compiler, you can use the Verilog
sources in any of the `builds/<ARCH>_<CPU>_verilator/Verilog_RTL`
directories-- build and run Verilog simulations, incorporate the
Verilog CPU into your own SoC, etc. This section describes additional
things you can do with a `bsc` compiler.
#### Building a Bluesim simulator
In any of the following directories:
builds/<ARCH>_<CPU>_bluesim
- `$ make compile simulator`
will compile and link a Bluesim executable. Then, you can `make test`
or `make isa_tests` as described above to run an individual ISA test
or run regressions on the full suite of relevant ISA tests.
#### Re-generating Verilog RTL
You can regenerate the Verilog RTL in any of the
`build/<ARCH>_<CPU>_verilator/` or `build/<ARCH>_<CPU>_iverilog/`
directories. Example:
$ cd builds/RV32ACIMU_<CPU>_verilator
$ make compile
#### Creating a new architecture configuration
[This documentation needs to be fleshed out.] The `builds/Resources`
directory contains some "include" files for Makefiles, and illustrate
the compile-time flags that determine the micro-architectural
configuration.
In addition, MIT's riscy-ooo code provides further configuration
controls, which can be found in:
Toooba/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
----------------------------------------------------------------

3
Tests/Run_regression.py
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@@ -41,8 +41,7 @@ num_executed = 0
num_passed = 0
# DEBUGGING ONLY: This exclude list allows skipping some specific test
# Tuba seems to hang on this test
exclude_list = ["rv64ud-p-move"]
exclude_list = []
# ================================================================

2
builds/RV64ADFIMSU_Toooba_verilator/Makefile → builds/RV64ACDFIMSU_Toooba_verilator/Makefile
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@@ -16,7 +16,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS)
# ================================================================
REPO ?= ../..
ARCH ?= RV64ADFIMSU
ARCH ?= RV64ACDFIMSU
# ================================================================
# RISC-V config macros passed into Bluespec 'bsc' compiler

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluDispToRegFifo.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluExeToFinFifo.v
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126
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkAluRegToExeFifo.v
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@@ -8,13 +8,13 @@
// Name I/O size props
// RDY_enq O 1
// RDY_deq O 1
// first O 390
// first O 422
// RDY_first O 1
// RDY_specUpdate_incorrectSpeculation O 1 const
// RDY_specUpdate_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// enq_x I 390
// enq_x I 422
// specUpdate_incorrectSpeculation_kill_all I 1
// specUpdate_incorrectSpeculation_kill_tag I 4
// specUpdate_correctSpeculation_mask I 12
@@ -69,7 +69,7 @@ module mkAluRegToExeFifo(CLK,
input RST_N;
// action method enq
input [389 : 0] enq_x;
input [421 : 0] enq_x;
input EN_enq;
output RDY_enq;
@@ -78,7 +78,7 @@ module mkAluRegToExeFifo(CLK,
output RDY_deq;
// value method first
output [389 : 0] first;
output [421 : 0] first;
output RDY_first;
// action method specUpdate_incorrectSpeculation
@@ -93,7 +93,7 @@ module mkAluRegToExeFifo(CLK,
output RDY_specUpdate_correctSpeculation;
// signals for module outputs
wire [389 : 0] first;
wire [421 : 0] first;
wire RDY_deq,
RDY_enq,
RDY_first,
@@ -105,8 +105,8 @@ module mkAluRegToExeFifo(CLK,
wire m_m_valid_0_lat_0$whas;
// register m_m_row_0
reg [377 : 0] m_m_row_0;
wire [377 : 0] m_m_row_0$D_IN;
reg [409 : 0] m_m_row_0;
wire [409 : 0] m_m_row_0$D_IN;
wire m_m_row_0$EN;
// register m_m_specBits_0_rl
@@ -162,15 +162,15 @@ module mkAluRegToExeFifo(CLK,
wire MUX_m_m_valid_0_dummy2_0$write_1__SEL_1;
// remaining internal signals
reg [20 : 0] CASE_enq_x_BITS_384_TO_382_0_enq_x_BITS_384_TO_ETC__q2,
CASE_m_m_row_0_BITS_372_TO_370_0_m_m_row_0_BIT_ETC__q5;
reg [11 : 0] CASE_enq_x_BITS_362_TO_351_1_enq_x_BITS_362_TO_ETC__q3,
CASE_m_m_row_0_BITS_350_TO_339_1_m_m_row_0_BIT_ETC__q6;
reg [2 : 0] CASE_enq_x_BITS_367_TO_365_0_enq_x_BITS_367_TO_ETC__q1,
CASE_m_m_row_0_BITS_355_TO_353_0_m_m_row_0_BIT_ETC__q4;
reg [20 : 0] CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5;
reg [11 : 0] CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6;
reg [2 : 0] CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4;
wire [11 : 0] IF_m_m_specBits_0_dummy2_0_read__62_AND_m_m_sp_ETC___d265,
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13,
sb__h10259,
sb__h10270,
upd__h2327;
wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6;
@@ -192,11 +192,11 @@ module mkAluRegToExeFifo(CLK,
// value method first
assign first =
{ m_m_row_0[377:373],
CASE_m_m_row_0_BITS_372_TO_370_0_m_m_row_0_BIT_ETC__q5,
m_m_row_0[351],
CASE_m_m_row_0_BITS_350_TO_339_1_m_m_row_0_BIT_ETC__q6,
m_m_row_0[338:0],
{ m_m_row_0[409:405],
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5,
m_m_row_0[383],
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6,
m_m_row_0[370:0],
IF_m_m_specBits_0_dummy2_0_read__62_AND_m_m_sp_ETC___d265 } ;
assign RDY_first = RDY_deq ;
@@ -266,15 +266,15 @@ module mkAluRegToExeFifo(CLK,
assign m_m_valid_0_lat_0$whas =
MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
assign m_m_specBits_0_lat_1$wget =
sb__h10259 & specUpdate_correctSpeculation_mask ;
sb__h10270 & specUpdate_correctSpeculation_mask ;
// register m_m_row_0
assign m_m_row_0$D_IN =
{ enq_x[389:385],
CASE_enq_x_BITS_384_TO_382_0_enq_x_BITS_384_TO_ETC__q2,
enq_x[363],
CASE_enq_x_BITS_362_TO_351_1_enq_x_BITS_362_TO_ETC__q3,
enq_x[350:12] } ;
{ enq_x[421:417],
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
enq_x[395],
CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
enq_x[382:12] } ;
assign m_m_row_0$EN = EN_enq ;
// register m_m_specBits_0_rl
@@ -325,40 +325,40 @@ module mkAluRegToExeFifo(CLK,
EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 =
m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl ;
assign sb__h10259 =
assign sb__h10270 =
m_m_specBits_0_dummy2_1$Q_OUT ?
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
12'd0 ;
assign upd__h2327 = m_m_specBits_0_lat_1$wget ;
always@(enq_x)
begin
case (enq_x[367:365])
case (enq_x[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_enq_x_BITS_367_TO_365_0_enq_x_BITS_367_TO_ETC__q1 =
enq_x[367:365];
default: CASE_enq_x_BITS_367_TO_365_0_enq_x_BITS_367_TO_ETC__q1 = 3'd7;
CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 =
enq_x[399:397];
default: CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 = 3'd7;
endcase
end
always@(enq_x or CASE_enq_x_BITS_367_TO_365_0_enq_x_BITS_367_TO_ETC__q1)
always@(enq_x or CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1)
begin
case (enq_x[384:382])
case (enq_x[416:414])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_enq_x_BITS_384_TO_382_0_enq_x_BITS_384_TO_ETC__q2 =
enq_x[384:364];
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
enq_x[416:396];
3'd4:
CASE_enq_x_BITS_384_TO_382_0_enq_x_BITS_384_TO_ETC__q2 =
{ enq_x[384:382],
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
{ enq_x[416:414],
9'h0AA,
enq_x[372:368],
CASE_enq_x_BITS_367_TO_365_0_enq_x_BITS_367_TO_ETC__q1,
enq_x[364] };
default: CASE_enq_x_BITS_384_TO_382_0_enq_x_BITS_384_TO_ETC__q2 =
enq_x[404:400],
CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
enq_x[396] };
default: CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
21'd1485482;
endcase
end
always@(enq_x)
begin
case (enq_x[362:351])
case (enq_x[394:383])
12'd1,
12'd2,
12'd3,
@@ -395,41 +395,41 @@ module mkAluRegToExeFifo(CLK,
12'd3858,
12'd3859,
12'd3860:
CASE_enq_x_BITS_362_TO_351_1_enq_x_BITS_362_TO_ETC__q3 =
enq_x[362:351];
default: CASE_enq_x_BITS_362_TO_351_1_enq_x_BITS_362_TO_ETC__q3 =
CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
enq_x[394:383];
default: CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
12'd2303;
endcase
end
always@(m_m_row_0)
begin
case (m_m_row_0[355:353])
case (m_m_row_0[387:385])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_m_m_row_0_BITS_355_TO_353_0_m_m_row_0_BIT_ETC__q4 =
m_m_row_0[355:353];
default: CASE_m_m_row_0_BITS_355_TO_353_0_m_m_row_0_BIT_ETC__q4 = 3'd7;
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 =
m_m_row_0[387:385];
default: CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 = 3'd7;
endcase
end
always@(m_m_row_0 or CASE_m_m_row_0_BITS_355_TO_353_0_m_m_row_0_BIT_ETC__q4)
always@(m_m_row_0 or CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4)
begin
case (m_m_row_0[372:370])
case (m_m_row_0[404:402])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_m_m_row_0_BITS_372_TO_370_0_m_m_row_0_BIT_ETC__q5 =
m_m_row_0[372:352];
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
m_m_row_0[404:384];
3'd4:
CASE_m_m_row_0_BITS_372_TO_370_0_m_m_row_0_BIT_ETC__q5 =
{ m_m_row_0[372:370],
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
{ m_m_row_0[404:402],
9'h0AA,
m_m_row_0[360:356],
CASE_m_m_row_0_BITS_355_TO_353_0_m_m_row_0_BIT_ETC__q4,
m_m_row_0[352] };
default: CASE_m_m_row_0_BITS_372_TO_370_0_m_m_row_0_BIT_ETC__q5 =
m_m_row_0[392:388],
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4,
m_m_row_0[384] };
default: CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
21'd1485482;
endcase
end
always@(m_m_row_0)
begin
case (m_m_row_0[350:339])
case (m_m_row_0[382:371])
12'd1,
12'd2,
12'd3,
@@ -466,9 +466,9 @@ module mkAluRegToExeFifo(CLK,
12'd3858,
12'd3859,
12'd3860:
CASE_m_m_row_0_BITS_350_TO_339_1_m_m_row_0_BIT_ETC__q6 =
m_m_row_0[350:339];
default: CASE_m_m_row_0_BITS_350_TO_339_1_m_m_row_0_BIT_ETC__q6 =
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
m_m_row_0[382:371];
default: CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
12'd2303;
endcase
end
@@ -498,7 +498,7 @@ module mkAluRegToExeFifo(CLK,
initial
begin
m_m_row_0 =
378'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
410'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_m_specBits_0_rl = 12'hAAA;
m_m_valid_0_rl = 1'h0;
end

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkBht.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBht.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkBoot_ROM.v
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27357
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
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File diff suppressed because it is too large Load Diff

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDCRqMshrWrapper.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDCRqMshrWrapper.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDPRqMshrWrapper.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDPRqMshrWrapper.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDPipeline.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDPipeline.v
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186
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDTlbSynth.v
View File

@@ -6797,11 +6797,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_4__ETC___d761 =
!m_ldTransRsFromPQ_data_0[4];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 =
m_ldTransRsFromPQ_data_0[6];
1'd1:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_4__ETC___d761 =
!m_ldTransRsFromPQ_data_1[4];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 =
m_ldTransRsFromPQ_data_1[6];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -6809,11 +6809,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 =
m_ldTransRsFromPQ_data_0[6];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_4__ETC___d761 =
!m_ldTransRsFromPQ_data_0[4];
1'd1:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_6_62_m_ETC___d765 =
m_ldTransRsFromPQ_data_1[6];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_4__ETC___d761 =
!m_ldTransRsFromPQ_data_1[4];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -6853,11 +6853,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_5_03_m_ETC___d806 =
m_ldTransRsFromPQ_data_0[5];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_7_72_m_ETC___d775 =
m_ldTransRsFromPQ_data_0[7];
1'd1:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_5_03_m_ETC___d806 =
m_ldTransRsFromPQ_data_1[5];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_7_72_m_ETC___d775 =
m_ldTransRsFromPQ_data_1[7];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -6865,11 +6865,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_7_72_m_ETC___d775 =
m_ldTransRsFromPQ_data_0[7];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_5_03_m_ETC___d806 =
m_ldTransRsFromPQ_data_0[5];
1'd1:
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_7_72_m_ETC___d775 =
m_ldTransRsFromPQ_data_1[7];
SEL_ARR_m_ldTransRsFromPQ_data_0_00_BIT_5_03_m_ETC___d806 =
m_ldTransRsFromPQ_data_1[5];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -6889,11 +6889,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 =
!m_ldTransRsFromPQ_data_0[10];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_9__ETC___d750 =
!m_ldTransRsFromPQ_data_0[9];
1'd1:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 =
!m_ldTransRsFromPQ_data_1[10];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_9__ETC___d750 =
!m_ldTransRsFromPQ_data_1[9];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -6901,11 +6901,11 @@ module mkDTlbSynth(CLK,
begin
case (m_ldTransRsFromPQ_deqP)
1'd0:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_9__ETC___d750 =
!m_ldTransRsFromPQ_data_0[9];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 =
!m_ldTransRsFromPQ_data_0[10];
1'd1:
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_9__ETC___d750 =
!m_ldTransRsFromPQ_data_1[9];
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_00_BIT_10_ETC___d743 =
!m_ldTransRsFromPQ_data_1[10];
endcase
end
always@(m_ldTransRsFromPQ_deqP or
@@ -8866,31 +8866,6 @@ module mkDTlbSynth(CLK,
4'd6;
endcase
end
always@(idx__h124884 or
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or
IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or
IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160)
begin
case (idx__h124884)
2'd0:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 ==
4'd1;
2'd1:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 ==
4'd1;
2'd2:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 ==
4'd1;
2'd3:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 ==
4'd1;
endcase
end
always@(idx__h124884 or
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or
@@ -8966,6 +8941,31 @@ module mkDTlbSynth(CLK,
4'd3;
endcase
end
always@(idx__h124884 or
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or
IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 or
IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160)
begin
case (idx__h124884)
2'd0:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 ==
4'd1;
2'd1:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 ==
4'd1;
2'd2:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_2_025_BITS_3_TO_0_106_EQ_0_107_O_ETC___d3132 ==
4'd1;
2'd3:
SEL_ARR_IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_ETC___d3169 =
IF_m_pendResp_3_027_BITS_3_TO_0_134_EQ_0_135_O_ETC___d3160 ==
4'd1;
endcase
end
always@(idx__h124884 or
IF_m_pendResp_0_021_BITS_3_TO_0_050_EQ_0_051_O_ETC___d3076 or
IF_m_pendResp_1_023_BITS_3_TO_0_078_EQ_0_079_O_ETC___d3104 or
@@ -9184,24 +9184,6 @@ module mkDTlbSynth(CLK,
m_pendInst_3[67];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
case (idx__h124884)
2'd0:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_0[66];
2'd1:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_1[66];
2'd2:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_2[66];
2'd3:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_3[66];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
@@ -9220,6 +9202,24 @@ module mkDTlbSynth(CLK,
m_pendInst_3[65];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
case (idx__h124884)
2'd0:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_0[66];
2'd1:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_1[66];
2'd2:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_2[66];
2'd3:
SEL_ARR_m_pendInst_0_23_BIT_66_335_m_pendInst__ETC___d3340 =
m_pendInst_3[66];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
@@ -9256,24 +9256,6 @@ module mkDTlbSynth(CLK,
m_pendInst_3[89:85];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
case (idx__h124884)
2'd0:
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_0[84:79];
2'd1:
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_1[84:79];
2'd2:
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_2[84:79];
2'd3:
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_3[84:79];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
@@ -9297,17 +9279,17 @@ module mkDTlbSynth(CLK,
begin
case (idx__h124884)
2'd0:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_0[77:73];
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_0[84:79];
2'd1:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_1[77:73];
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_1[84:79];
2'd2:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_2[77:73];
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_2[84:79];
2'd3:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_3[77:73];
SEL_ARR_m_pendInst_0_23_BITS_84_TO_79_264_m_pe_ETC___d3269 =
m_pendInst_3[84:79];
endcase
end
always@(idx__h124884 or
@@ -9328,6 +9310,24 @@ module mkDTlbSynth(CLK,
m_pendInst_3[0];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin
case (idx__h124884)
2'd0:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_0[77:73];
2'd1:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_1[77:73];
2'd2:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_2[77:73];
2'd3:
SEL_ARR_m_pendInst_0_23_BITS_77_TO_73_282_m_pe_ETC___d3287 =
m_pendInst_3[77:73];
endcase
end
always@(idx__h124884 or
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
begin

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDirPredictor.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDirPredictor.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDivExecQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDivExecQ.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleDiv.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleDiv.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleFMA.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleFMA.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleSqrt.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDoubleSqrt.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkDummyStoreBuffer.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkDummyStoreBuffer.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkEpochManager.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkEpochManager.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_AXI4.v
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14619
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFetchStage.v
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File diff suppressed because it is too large Load Diff

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFmaExecQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFmaExecQ.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivDispToRegFifo.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFpuMulDivRegToExeFifo.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectGHistReg.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectGHistReg.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectPred.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSelectPred.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkGShareGHistReg.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGShareGHistReg.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkGSharePred.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkGSharePred.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkIBankWrapper.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIBankWrapper.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkICRqMshrWrapper.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkICRqMshrWrapper.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkICoCache.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkICoCache.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkIPRqMshrWrapper.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIPRqMshrWrapper.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkIPipeline.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkIPipeline.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkITlb.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkITlb.v
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1052
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkL2Tlb.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkL2Tlb.v
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File diff suppressed because it is too large Load Diff

1724
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLLCache.v
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File diff suppressed because it is too large Load Diff

150
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLLPipeline.v
View File

@@ -1376,12 +1376,12 @@ module mkLLPipeline(CLK,
// remaining internal signals
reg [975 : 0] IF_send_r_BITS_583_TO_582_645_EQ_0_646_THEN_m__ETC___d3902;
reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5,
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3;
reg [69 : 0] CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4,
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21;
reg [47 : 0] y_avValue_info_tag__h196519;
reg [3 : 0] CASE_send_r_BITS_583_TO_582_0_send_r_BITS_583__ETC__q2,
SEL_ARR_IF_IF_m_pipe_enq2Mat_lat_0_whas__77_TH_ETC___d3536;
reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4,
reg [1 : 0] CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12,
@@ -1393,7 +1393,7 @@ module mkLLPipeline(CLK,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8,
@@ -3984,11 +3984,11 @@ module mkLLPipeline(CLK,
// inlined wires
assign m_pipe_enq2Mat_lat_0$wget =
{ 1'd1,
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5,
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4,
IF_IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypa_ETC___d2113 } ;
assign m_pipe_enq2Mat_lat_2$wget =
{ 1'd1,
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3,
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21,
IF_send_r_BITS_583_TO_582_645_EQ_0_646_THEN_m__ETC___d3923 } ;
assign m_pipe_mat2Out_lat_0$wget =
{ deqWrite_swapRq[4],
@@ -5957,7 +5957,7 @@ module mkLLPipeline(CLK,
IF_m_pipe_bypass_whas__574_THEN_m_pipe_bypass__ETC___d1611 ||
m_pipe_enq2Mat_rl[517],
m_pipe_enq2Mat_rl[516:4],
CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4,
CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3,
m_pipe_enq2Mat_rl[1:0] } ;
assign IF_IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m__ETC___d2634 =
(IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 ==
@@ -10177,38 +10177,25 @@ module mkLLPipeline(CLK,
{ 2'd2, send_r[517:516] };
endcase
end
always@(send_r)
begin
case (send_r[583:582])
2'd0:
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 =
{ 2'd0, send_r[67:0] };
2'd1:
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 =
{ send_r[583:582], 3'h2, send_r[579:516], send_r[0] };
default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q3 =
{ 2'd2, send_r[581:518], send_r[3:0] };
endcase
end
always@(m_pipe_enq2Mat_rl)
begin
case (m_pipe_enq2Mat_rl[3:2])
2'd0, 2'd1:
CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 =
CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 =
m_pipe_enq2Mat_rl[3:2];
default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q4 = 2'd2;
default: CASE_m_pipe_enq2Mat_rl_BITS_3_TO_2_0_m_pipe_en_ETC__q3 = 2'd2;
endcase
end
always@(m_pipe_enq2Mat_rl)
begin
case (m_pipe_enq2Mat_rl[1563:1562])
2'd0:
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 =
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 =
{ 2'd0, m_pipe_enq2Mat_rl[1561:1494] };
2'd1:
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 =
CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 =
m_pipe_enq2Mat_rl[1563:1494];
default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q5 =
default: CASE_m_pipe_enq2Mat_rl_BITS_1563_TO_1562_0_0_C_ETC__q4 =
{ 2'd2, m_pipe_enq2Mat_rl[1561:1494] };
endcase
end
@@ -10591,10 +10578,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3189;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3195;
endcase
end
@@ -10604,10 +10591,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3203;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3209;
endcase
end
@@ -10617,10 +10604,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3217;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3223;
endcase
end
@@ -10630,10 +10617,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3231;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3237;
endcase
end
@@ -10643,10 +10630,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3245;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3251;
endcase
end
@@ -10656,10 +10643,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3259;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3265;
endcase
end
@@ -10669,10 +10656,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3273;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3279;
endcase
end
@@ -10682,10 +10669,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3287;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3293;
endcase
end
@@ -10695,10 +10682,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3301;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3307;
endcase
end
@@ -10708,10 +10695,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3315;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3321;
endcase
end
@@ -10721,10 +10708,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3329;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3335;
endcase
end
@@ -10734,10 +10721,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3343;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3349;
endcase
end
@@ -10747,10 +10734,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3357;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3363;
endcase
end
@@ -10760,10 +10747,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3371;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3377;
endcase
end
@@ -10773,10 +10760,10 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3385;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3391;
endcase
end
@@ -10786,14 +10773,15 @@ module mkLLPipeline(CLK,
begin
case (x__h187917)
1'd0:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3399;
1'd1:
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 =
IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3405;
endcase
end
always@(way__h182888 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8 or
@@ -10808,58 +10796,57 @@ module mkLLPipeline(CLK,
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20 or
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21)
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20)
begin
case (way__h182888)
4'd0:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q5;
4'd1:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q6;
4'd2:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q7;
4'd3:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q8;
4'd4:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q9;
4'd5:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q10;
4'd6:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q11;
4'd7:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q12;
4'd8:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q13;
4'd9:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q14;
4'd10:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q15;
4'd11:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q16;
4'd12:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q17;
4'd13:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q18;
4'd14:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q19;
4'd15:
SEL_ARR_SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_rea_ETC___d3409 =
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q21;
CASE_x87917_0_IF_m_pipe_enq2Mat_dummy2_1_read__ETC__q20;
endcase
end
always@(way__h182888 or
@@ -11207,6 +11194,19 @@ module mkLLPipeline(CLK,
IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3616;
endcase
end
always@(send_r)
begin
case (send_r[583:582])
2'd0:
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 =
{ 2'd0, send_r[67:0] };
2'd1:
CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 =
{ send_r[583:582], 3'h2, send_r[579:516], send_r[0] };
default: CASE_send_r_BITS_583_TO_582_0_0_CONCAT_send_r__ETC__q21 =
{ 2'd2, send_r[581:518], send_r[3:0] };
endcase
end
// handling of inlined registers

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLSQIssueLdQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLSQIssueLdQ.v
View File

7738
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkLastLvCRqMshr.v
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File diff suppressed because it is too large Load Diff

58
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMMIOInst.v
View File

@@ -337,6 +337,11 @@ module mkMMIOInst(CLK,
respQ_enqReq_dummy2_2$EN,
respQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
// rule scheduling signals
wire CAN_FIRE_RL_pendQ_canonicalize,
CAN_FIRE_RL_pendQ_clearReq_canon,
@@ -374,7 +379,6 @@ module mkMMIOInst(CLK,
WILL_FIRE_toCore_setHtifAddrs;
// remaining internal signals
wire [1 : 0] IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276;
wire IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13,
IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91,
NOT_pendQ_enqReq_dummy2_2_read__34_49_OR_IF_pe_ETC___d259,
@@ -388,10 +392,12 @@ module mkMMIOInst(CLK,
// value method getFetchTarget
assign getFetchTarget =
(getFetchTarget_phyPc[63:3] >= 61'd512 &&
getFetchTarget_phyPc[63:3] < 61'd1024) ?
2'd1 :
IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 ;
(getFetchTarget_phyPc[63:3] >= 61'd268435456 &&
getFetchTarget_phyPc[63:3] < 61'd301989888 &&
getFetchTarget_phyPc[63:3] != toHostAddr &&
getFetchTarget_phyPc[63:3] != fromHostAddr) ?
2'd0 :
2'd1 ;
assign RDY_getFetchTarget = 1'd1 ;
// action method bootRomReq
@@ -580,6 +586,37 @@ module mkMMIOInst(CLK,
.EN(respQ_enqReq_dummy2_2$EN),
.Q_OUT(respQ_enqReq_dummy2_2$Q_OUT));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_reqQ_canonicalize
assign CAN_FIRE_RL_reqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_reqQ_canonicalize = 1'd1 ;
@@ -838,13 +875,12 @@ module mkMMIOInst(CLK,
assign respQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign respQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_getFetchTarget_phyPc_BITS_63_TO_3_61_UL_ETC___d276 =
(getFetchTarget_phyPc[63:3] >= 61'd268435456 &&
getFetchTarget_phyPc[63:3] != toHostAddr &&
getFetchTarget_phyPc[63:3] != fromHostAddr) ?
2'd0 :
2'd2 ;
assign IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13 =
EN_bootRomReq ? reqQ_enqReq_lat_0$wget[65] : reqQ_enqReq_rl[65] ;
assign IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91 =

5
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemDispToRegFifo.v
View File

@@ -101,7 +101,6 @@ module mkMemDispToRegFifo(CLK,
RDY_specUpdate_incorrectSpeculation;
// inlined wires
wire [11 : 0] m_m_specBits_0_lat_1$wget;
wire m_m_valid_0_lat_0$whas;
// register m_m_row_0
@@ -255,8 +254,6 @@ module mkMemDispToRegFifo(CLK,
// inlined wires
assign m_m_valid_0_lat_0$whas =
MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
assign m_m_specBits_0_lat_1$wget =
sb__h6991 & specUpdate_correctSpeculation_mask ;
// register m_m_row_0
assign m_m_row_0$D_IN = enq_x[97:12] ;
@@ -314,7 +311,7 @@ module mkMemDispToRegFifo(CLK,
m_m_specBits_0_dummy2_1$Q_OUT ?
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
12'd0 ;
assign upd__h2327 = m_m_specBits_0_lat_1$wget ;
assign upd__h2327 = sb__h6991 & specUpdate_correctSpeculation_mask ;
// handling of inlined registers

1757
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemLoader.v
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File diff suppressed because it is too large Load Diff

5
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMemRegToExeFifo.v
View File

@@ -101,7 +101,6 @@ module mkMemRegToExeFifo(CLK,
RDY_specUpdate_incorrectSpeculation;
// inlined wires
wire [11 : 0] m_m_specBits_0_lat_1$wget;
wire m_m_valid_0_lat_0$whas;
// register m_m_row_0
@@ -255,8 +254,6 @@ module mkMemRegToExeFifo(CLK,
// inlined wires
assign m_m_valid_0_lat_0$whas =
MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
assign m_m_specBits_0_lat_1$wget =
sb__h6440 & specUpdate_correctSpeculation_mask ;
// register m_m_row_0
assign m_m_row_0$D_IN = enq_x[192:12] ;
@@ -314,7 +311,7 @@ module mkMemRegToExeFifo(CLK,
m_m_specBits_0_dummy2_1$Q_OUT ?
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
12'd0 ;
assign upd__h2327 = m_m_specBits_0_lat_1$wget ;
assign upd__h2327 = sb__h6440 & specUpdate_correctSpeculation_mask ;
// handling of inlined registers

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Controller.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Model.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMem_Model.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMinimumExecQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMinimumExecQ.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkMulExecQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkMulExecQ.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkNullTransCache.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkNullTransCache.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkPLIC_16_2_7.v
View File

2649
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v
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File diff suppressed because it is too large Load Diff

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkRFileSynth.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRFileSynth.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkRas.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRas.v
View File

21824
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkRegRenamingTable.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRegRenamingTable.v
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File diff suppressed because it is too large Load Diff

59601
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v
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File diff suppressed because it is too large Load Diff

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationAlu.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationFpuMulDiv.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationFpuMulDiv.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationMem.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReservationStationMem.v
View File

361
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkRobRowSynth.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRobRowSynth.v
View File

@@ -7,7 +7,7 @@
// Ports:
// Name I/O size props
// RDY_write_enq O 1 const
// read_deq O 187
// read_deq O 283
// RDY_read_deq O 1 const
// RDY_setLSQAtCommitNotified O 1 const
// RDY_setExecuted_deqLSQ O 1 const
@@ -19,12 +19,14 @@
// RDY_getOrigPC O 1 const
// getOrigPredPC O 64
// RDY_getOrigPredPC O 1 const
// getOrig_Inst O 32 reg
// RDY_getOrig_Inst O 1 const
// dependsOn_wrongSpec O 1
// RDY_dependsOn_wrongSpec O 1 const
// RDY_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// write_enq_x I 187
// write_enq_x I 283
// setExecuted_deqLSQ_cause I 5
// setExecuted_deqLSQ_ld_killed I 3
// setExecuted_doFinishAlu_0_set_csrData I 65
@@ -108,6 +110,9 @@ module mkRobRowSynth(CLK,
getOrigPredPC,
RDY_getOrigPredPC,
getOrig_Inst,
RDY_getOrig_Inst,
dependsOn_wrongSpec_tag,
dependsOn_wrongSpec,
RDY_dependsOn_wrongSpec,
@@ -119,12 +124,12 @@ module mkRobRowSynth(CLK,
input RST_N;
// action method write_enq
input [186 : 0] write_enq_x;
input [282 : 0] write_enq_x;
input EN_write_enq;
output RDY_write_enq;
// value method read_deq
output [186 : 0] read_deq;
output [282 : 0] read_deq;
output RDY_read_deq;
// action method setLSQAtCommitNotified
@@ -169,6 +174,10 @@ module mkRobRowSynth(CLK,
output [63 : 0] getOrigPredPC;
output RDY_getOrigPredPC;
// value method getOrig_Inst
output [31 : 0] getOrig_Inst;
output RDY_getOrig_Inst;
// value method dependsOn_wrongSpec
input [3 : 0] dependsOn_wrongSpec_tag;
output dependsOn_wrongSpec;
@@ -180,12 +189,14 @@ module mkRobRowSynth(CLK,
output RDY_correctSpeculation;
// signals for module outputs
wire [186 : 0] read_deq;
wire [282 : 0] read_deq;
wire [63 : 0] getOrigPC, getOrigPredPC;
wire [31 : 0] getOrig_Inst;
wire RDY_correctSpeculation,
RDY_dependsOn_wrongSpec,
RDY_getOrigPC,
RDY_getOrigPredPC,
RDY_getOrig_Inst,
RDY_read_deq,
RDY_setExecuted_deqLSQ,
RDY_setExecuted_doFinishAlu_0_set,
@@ -249,6 +260,11 @@ module mkRobRowSynth(CLK,
reg m_nonMMIOStDone_rl;
wire m_nonMMIOStDone_rl$D_IN, m_nonMMIOStDone_rl$EN;
// register m_orig_inst
reg [31 : 0] m_orig_inst;
wire [31 : 0] m_orig_inst$D_IN;
wire m_orig_inst$EN;
// register m_pc
reg [63 : 0] m_pc;
wire [63 : 0] m_pc$D_IN;
@@ -273,6 +289,11 @@ module mkRobRowSynth(CLK,
wire [5 : 0] m_trap_rl$D_IN;
wire m_trap_rl$EN;
// register m_tval_rl
reg [63 : 0] m_tval_rl;
wire [63 : 0] m_tval_rl$D_IN;
wire m_tval_rl$EN;
// register m_will_dirty_fpu_state
reg m_will_dirty_fpu_state;
wire m_will_dirty_fpu_state$D_IN, m_will_dirty_fpu_state$EN;
@@ -402,6 +423,15 @@ module mkRobRowSynth(CLK,
// ports of submodule m_trap_dummy2_2
wire m_trap_dummy2_2$D_IN, m_trap_dummy2_2$EN, m_trap_dummy2_2$Q_OUT;
// ports of submodule m_tval_dummy2_0
wire m_tval_dummy2_0$D_IN, m_tval_dummy2_0$EN, m_tval_dummy2_0$Q_OUT;
// ports of submodule m_tval_dummy2_1
wire m_tval_dummy2_1$D_IN, m_tval_dummy2_1$EN, m_tval_dummy2_1$Q_OUT;
// ports of submodule m_tval_dummy2_2
wire m_tval_dummy2_2$D_IN, m_tval_dummy2_2$EN, m_tval_dummy2_2$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_m_fflags_canon,
CAN_FIRE_RL_m_ldKilled_canon,
@@ -413,6 +443,7 @@ module mkRobRowSynth(CLK,
CAN_FIRE_RL_m_setPcWires,
CAN_FIRE_RL_m_spec_bits_canon,
CAN_FIRE_RL_m_trap_canon,
CAN_FIRE_RL_m_tval_canon,
CAN_FIRE_correctSpeculation,
CAN_FIRE_setExecuted_deqLSQ,
CAN_FIRE_setExecuted_doFinishAlu_0_set,
@@ -431,6 +462,7 @@ module mkRobRowSynth(CLK,
WILL_FIRE_RL_m_setPcWires,
WILL_FIRE_RL_m_spec_bits_canon,
WILL_FIRE_RL_m_trap_canon,
WILL_FIRE_RL_m_tval_canon,
WILL_FIRE_correctSpeculation,
WILL_FIRE_setExecuted_deqLSQ,
WILL_FIRE_setExecuted_doFinishAlu_0_set,
@@ -442,25 +474,26 @@ module mkRobRowSynth(CLK,
// remaining internal signals
reg [11 : 0] CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8;
CASE_write_enq_x_BITS_180_TO_169_1_write_enq_x_ETC__q8;
reg [3 : 0] CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1,
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2,
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q4,
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5,
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6;
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q5,
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q6;
reg [1 : 0] CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7;
wire [117 : 0] m_csr_42_BIT_12_43_CONCAT_IF_m_csr_42_BIT_12_4_ETC___d614;
wire [103 : 0] m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d613;
wire [65 : 0] IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559;
wire [63 : 0] IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199;
wire [11 : 0] IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281,
bs__h30484,
sb__h30519,
upd__h16356;
wire [186 : 0] m_iType_54_CONCAT_m_csr_55_BIT_12_56_CONCAT_IF_ETC___d636;
wire [168 : 0] m_claimed_phy_reg_32_CONCAT_m_trap_dummy2_0_re_ETC___d635;
wire [65 : 0] IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_9_ETC___d580;
wire [63 : 0] IF_m_ppc_vaddr_csrData_dummy2_0_read__93_AND_m_ETC___d308,
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d207,
IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d209,
x__h26679;
wire [11 : 0] IF_m_spec_bits_lat_1_whas__85_THEN_m_spec_bits_ETC___d291,
bs__h32816,
sb__h32851,
upd__h17952;
wire [4 : 0] IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d154,
x_read_deq_fflags__h23633;
x_read_deq_fflags__h25872;
wire [3 : 0] IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d153,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d131,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d132,
@@ -474,14 +507,14 @@ module mkRobRowSynth(CLK,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d148,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d150,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d152;
wire [1 : 0] IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246;
wire IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236,
IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188,
IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224,
wire [1 : 0] IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d256;
wire IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d246,
IF_m_memAccessAtCommit_lat_1_whas__61_THEN_m_m_ETC___d267,
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d187,
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d196,
IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d189,
IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d198,
IF_m_rob_inst_state_lat_3_whas__22_THEN_m_rob__ETC___d234,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d109,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d116,
@@ -491,11 +524,11 @@ module mkRobRowSynth(CLK,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95,
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d655,
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d663,
NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293,
m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576,
m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524;
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d677,
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d685,
NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_94_O_ETC___d303,
m_rob_inst_state_dummy2_0_read__86_AND_m_rob_i_ETC___d597,
m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538;
// action method write_enq
assign RDY_write_enq = 1'd1 ;
@@ -505,8 +538,8 @@ module mkRobRowSynth(CLK,
// value method read_deq
assign read_deq =
{ m_pc,
m_iType,
m_csr_42_BIT_12_43_CONCAT_IF_m_csr_42_BIT_12_4_ETC___d614 } ;
m_orig_inst,
m_iType_54_CONCAT_m_csr_55_BIT_12_56_CONCAT_IF_ETC___d636 } ;
assign RDY_read_deq = 1'd1 ;
// action method setLSQAtCommitNotified
@@ -548,14 +581,18 @@ module mkRobRowSynth(CLK,
// value method getOrigPredPC
assign getOrigPredPC =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 ||
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_94_O_ETC___d303 ||
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ?
IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 :
IF_m_ppc_vaddr_csrData_dummy2_0_read__93_AND_m_ETC___d308 :
64'd0 ;
assign RDY_getOrigPredPC = 1'd1 ;
// value method getOrig_Inst
assign getOrig_Inst = m_orig_inst ;
assign RDY_getOrig_Inst = 1'd1 ;
// value method dependsOn_wrongSpec
assign dependsOn_wrongSpec = bs__h30484[dependsOn_wrongSpec_tag] ;
assign dependsOn_wrongSpec = bs__h32816[dependsOn_wrongSpec_tag] ;
assign RDY_dependsOn_wrongSpec = 1'd1 ;
// action method correctSpeculation
@@ -734,6 +771,24 @@ module mkRobRowSynth(CLK,
.EN(m_trap_dummy2_2$EN),
.Q_OUT(m_trap_dummy2_2$Q_OUT));
// submodule m_tval_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_tval_dummy2_0(.CLK(CLK),
.D_IN(m_tval_dummy2_0$D_IN),
.EN(m_tval_dummy2_0$EN),
.Q_OUT(m_tval_dummy2_0$Q_OUT));
// submodule m_tval_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_tval_dummy2_1(.CLK(CLK),
.D_IN(m_tval_dummy2_1$D_IN),
.EN(m_tval_dummy2_1$EN),
.Q_OUT(m_tval_dummy2_1$Q_OUT));
// submodule m_tval_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_tval_dummy2_2(.CLK(CLK),
.D_IN(m_tval_dummy2_2$D_IN),
.EN(m_tval_dummy2_2$EN),
.Q_OUT(m_tval_dummy2_2$Q_OUT));
// rule RL_m_setPcWires
assign CAN_FIRE_RL_m_setPcWires = 1'd1 ;
assign WILL_FIRE_RL_m_setPcWires = 1'd1 ;
@@ -742,6 +797,10 @@ module mkRobRowSynth(CLK,
assign CAN_FIRE_RL_m_trap_canon = 1'd1 ;
assign WILL_FIRE_RL_m_trap_canon = 1'd1 ;
// rule RL_m_tval_canon
assign CAN_FIRE_RL_m_tval_canon = 1'd1 ;
assign WILL_FIRE_RL_m_tval_canon = 1'd1 ;
// rule RL_m_ppc_vaddr_csrData_canon
assign CAN_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
assign WILL_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
@@ -781,10 +840,10 @@ module mkRobRowSynth(CLK,
assign m_trap_lat_0$whas =
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[4] ;
assign m_trap_lat_2$wget =
{ write_enq_x[103:102],
write_enq_x[102] ?
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 :
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 } ;
{ write_enq_x[167:166],
write_enq_x[166] ?
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q5 :
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q6 } ;
assign m_ppc_vaddr_csrData_lat_0$wget =
setExecuted_doFinishAlu_0_set_csrData[64] ?
{ 2'd2, setExecuted_doFinishAlu_0_set_csrData[63:0] } :
@@ -803,13 +862,13 @@ module mkRobRowSynth(CLK,
setExecuted_doFinishMem_non_mmio_st_done ;
// register m_claimed_phy_reg
assign m_claimed_phy_reg$D_IN = write_enq_x[104] ;
assign m_claimed_phy_reg$D_IN = write_enq_x[168] ;
assign m_claimed_phy_reg$EN = EN_write_enq ;
// register m_csr
assign m_csr$D_IN =
{ write_enq_x[117],
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 } ;
{ write_enq_x[181],
CASE_write_enq_x_BITS_180_TO_169_1_write_enq_x_ETC__q8 } ;
assign m_csr$EN = EN_write_enq ;
// register m_epochIncremented
@@ -826,13 +885,13 @@ module mkRobRowSynth(CLK,
assign m_fflags_rl$EN = 1'd1 ;
// register m_iType
assign m_iType$D_IN = write_enq_x[122:118] ;
assign m_iType$D_IN = write_enq_x[186:182] ;
assign m_iType$EN = EN_write_enq ;
// register m_ldKilled_rl
assign m_ldKilled_rl$D_IN =
{ IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236,
IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246 } ;
{ IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d246,
IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d256 } ;
assign m_ldKilled_rl$EN = 1'd1 ;
// register m_lsqAtCommitNotified_rl
@@ -847,7 +906,7 @@ module mkRobRowSynth(CLK,
// register m_memAccessAtCommit_rl
assign m_memAccessAtCommit_rl$D_IN =
IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257 ;
IF_m_memAccessAtCommit_lat_1_whas__61_THEN_m_m_ETC___d267 ;
assign m_memAccessAtCommit_rl$EN = 1'd1 ;
// register m_nonMMIOStDone_rl
@@ -858,18 +917,22 @@ module mkRobRowSynth(CLK,
m_nonMMIOStDone_rl) ;
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
// register m_orig_inst
assign m_orig_inst$D_IN = write_enq_x[218:187] ;
assign m_orig_inst$EN = EN_write_enq ;
// register m_pc
assign m_pc$D_IN = write_enq_x[186:123] ;
assign m_pc$D_IN = write_enq_x[282:219] ;
assign m_pc$EN = EN_write_enq ;
// register m_ppc_vaddr_csrData_rl
assign m_ppc_vaddr_csrData_rl$D_IN =
{ IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179 ?
{ IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d189 ?
2'd0 :
(IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188 ?
(IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d198 ?
2'd1 :
2'd2),
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199 } ;
IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d209 } ;
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
// register m_rob_inst_state_rl
@@ -877,14 +940,14 @@ module mkRobRowSynth(CLK,
EN_write_enq ?
write_enq_x[25] :
m_rob_inst_state_lat_4$whas ||
IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224 ;
IF_m_rob_inst_state_lat_3_whas__22_THEN_m_rob__ETC___d234 ;
assign m_rob_inst_state_rl$EN = 1'd1 ;
// register m_spec_bits_rl
assign m_spec_bits_rl$D_IN =
EN_correctSpeculation ?
upd__h16356 :
IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 ;
upd__h17952 :
IF_m_spec_bits_lat_1_whas__85_THEN_m_spec_bits_ETC___d291 ;
assign m_spec_bits_rl$EN = 1'd1 ;
// register m_trap_rl
@@ -895,6 +958,10 @@ module mkRobRowSynth(CLK,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d154 } ;
assign m_trap_rl$EN = 1'd1 ;
// register m_tval_rl
assign m_tval_rl$D_IN = EN_write_enq ? write_enq_x[161:98] : m_tval_rl ;
assign m_tval_rl$EN = 1'd1 ;
// register m_will_dirty_fpu_state
assign m_will_dirty_fpu_state$D_IN = write_enq_x[26] ;
assign m_will_dirty_fpu_state$EN = EN_write_enq ;
@@ -1008,6 +1075,18 @@ module mkRobRowSynth(CLK,
assign m_trap_dummy2_2$D_IN = 1'd1 ;
assign m_trap_dummy2_2$EN = EN_write_enq ;
// submodule m_tval_dummy2_0
assign m_tval_dummy2_0$D_IN = 1'b0 ;
assign m_tval_dummy2_0$EN = 1'b0 ;
// submodule m_tval_dummy2_1
assign m_tval_dummy2_1$D_IN = 1'b0 ;
assign m_tval_dummy2_1$EN = 1'b0 ;
// submodule m_tval_dummy2_2
assign m_tval_dummy2_2$D_IN = 1'd1 ;
assign m_tval_dummy2_2$EN = EN_write_enq ;
// remaining internal signals
assign IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d153 =
(EN_write_enq ?
@@ -1099,82 +1178,82 @@ module mkRobRowSynth(CLK,
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d53 ?
4'd1 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d150) ;
assign IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559 =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 ||
assign IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_9_ETC___d580 =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_94_O_ETC___d303 ||
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ?
{ 2'd0,
IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 } :
IF_m_ppc_vaddr_csrData_dummy2_0_read__93_AND_m_ETC___d308 } :
{ (m_ppc_vaddr_csrData_rl[65:64] == 2'd1) ?
m_ppc_vaddr_csrData_rl[65:64] :
2'd2,
m_ppc_vaddr_csrData_rl[63:0] } ;
assign IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236 =
assign IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d246 =
!EN_write_enq &&
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[2] :
m_ldKilled_rl[2]) ;
assign IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246 =
assign IF_m_ldKilled_lat_1_whas__37_THEN_m_ldKilled_l_ETC___d256 =
EN_write_enq ?
2'b10 :
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[1:0] :
m_ldKilled_rl[1:0]) ;
assign IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257 =
assign IF_m_memAccessAtCommit_lat_1_whas__61_THEN_m_m_ETC___d267 =
EN_write_enq ?
write_enq_x[122:118] == 5'd14 :
write_enq_x[186:182] == 5'd14 :
(EN_setExecuted_doFinishMem ?
setExecuted_doFinishMem_access_at_commit :
m_memAccessAtCommit_rl) ;
assign IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 =
assign IF_m_ppc_vaddr_csrData_dummy2_0_read__93_AND_m_ETC___d308 =
(m_ppc_vaddr_csrData_dummy2_0$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_1$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_2$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_3$Q_OUT) ?
m_ppc_vaddr_csrData_rl[63:0] :
64'd0 ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d187 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[65:64] == 2'd0 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[65:64] == 2'd0 :
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d196 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[65:64] == 2'd1 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[65:64] == 2'd1 :
m_ppc_vaddr_csrData_rl[65:64] == 2'd1) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197 =
assign IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d207 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[63:0] :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[63:0] :
m_ppc_vaddr_csrData_rl[63:0]) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179 =
assign IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d189 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[65:64] == 2'd0 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[65:64] == 2'd0 :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188 =
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d187) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d198 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[65:64] == 2'd1 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[65:64] == 2'd1 :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199 =
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d196) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__67_THEN_m_p_ETC___d209 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[63:0] :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[63:0] :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197) ;
assign IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224 =
IF_m_ppc_vaddr_csrData_lat_1_whas__75_THEN_m_p_ETC___d207) ;
assign IF_m_rob_inst_state_lat_3_whas__22_THEN_m_rob__ETC___d234 =
EN_setExecuted_deqLSQ ||
EN_setExecuted_doFinishFpuMulDiv_0_set ||
EN_setExecuted_doFinishAlu_1_set ||
EN_setExecuted_doFinishAlu_0_set ||
m_rob_inst_state_rl ;
assign IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 =
assign IF_m_spec_bits_lat_1_whas__85_THEN_m_spec_bits_ETC___d291 =
EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102 =
EN_write_enq ?
@@ -1235,47 +1314,32 @@ module mkRobRowSynth(CLK,
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd7 :
m_trap_rl[3:0] == 4'd7) ;
assign NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d655 =
assign NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d677 =
m_csr[12] != setExecuted_doFinishAlu_0_set_csrData[64] ;
assign NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d663 =
assign NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d685 =
m_csr[12] != setExecuted_doFinishAlu_1_set_csrData[64] ;
assign NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 =
assign NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_94_O_ETC___d303 =
!m_ppc_vaddr_csrData_dummy2_0$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_1$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_2$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_3$Q_OUT ;
assign bs__h30484 =
assign bs__h32816 =
(m_spec_bits_dummy2_0$Q_OUT && m_spec_bits_dummy2_1$Q_OUT &&
m_spec_bits_dummy2_2$Q_OUT) ?
m_spec_bits_rl :
12'd0 ;
assign m_csr_42_BIT_12_43_CONCAT_IF_m_csr_42_BIT_12_4_ETC___d614 =
{ m_csr[12],
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
m_claimed_phy_reg,
m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d613 } ;
assign m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576 =
m_rob_inst_state_dummy2_0$Q_OUT &&
m_rob_inst_state_dummy2_1$Q_OUT &&
m_rob_inst_state_dummy2_2$Q_OUT &&
m_rob_inst_state_dummy2_3$Q_OUT &&
m_rob_inst_state_dummy2_4$Q_OUT &&
m_rob_inst_state_dummy2_5$Q_OUT &&
m_rob_inst_state_rl ;
assign m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524 =
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5] ;
assign m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d613 =
{ m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524,
assign m_claimed_phy_reg_32_CONCAT_m_trap_dummy2_0_re_ETC___d635 =
{ m_claimed_phy_reg,
m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538,
m_trap_rl[4],
m_trap_rl[4] ?
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1 :
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2,
IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559,
x_read_deq_fflags__h23633,
x__h26679,
IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__93_9_ETC___d580,
x_read_deq_fflags__h25872,
m_will_dirty_fpu_state,
m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576,
m_rob_inst_state_dummy2_0_read__86_AND_m_rob_i_ETC___d597,
m_lsqTag,
m_ldKilled_dummy2_0$Q_OUT && m_ldKilled_dummy2_1$Q_OUT &&
m_ldKilled_rl[2],
@@ -1291,13 +1355,35 @@ module mkRobRowSynth(CLK,
m_nonMMIOStDone_dummy2_1$Q_OUT &&
m_nonMMIOStDone_rl,
m_epochIncremented,
bs__h30484 } ;
assign sb__h30519 =
bs__h32816 } ;
assign m_iType_54_CONCAT_m_csr_55_BIT_12_56_CONCAT_IF_ETC___d636 =
{ m_iType,
m_csr[12],
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
m_claimed_phy_reg_32_CONCAT_m_trap_dummy2_0_re_ETC___d635 } ;
assign m_rob_inst_state_dummy2_0_read__86_AND_m_rob_i_ETC___d597 =
m_rob_inst_state_dummy2_0$Q_OUT &&
m_rob_inst_state_dummy2_1$Q_OUT &&
m_rob_inst_state_dummy2_2$Q_OUT &&
m_rob_inst_state_dummy2_3$Q_OUT &&
m_rob_inst_state_dummy2_4$Q_OUT &&
m_rob_inst_state_dummy2_5$Q_OUT &&
m_rob_inst_state_rl ;
assign m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538 =
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5] ;
assign sb__h32851 =
m_spec_bits_dummy2_2$Q_OUT ?
IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 :
IF_m_spec_bits_lat_1_whas__85_THEN_m_spec_bits_ETC___d291 :
12'd0 ;
assign upd__h16356 = sb__h30519 & correctSpeculation_mask ;
assign x_read_deq_fflags__h23633 =
assign upd__h17952 = sb__h32851 & correctSpeculation_mask ;
assign x__h26679 =
(m_tval_dummy2_0$Q_OUT && m_tval_dummy2_1$Q_OUT &&
m_tval_dummy2_2$Q_OUT) ?
m_tval_rl :
64'd0 ;
assign x_read_deq_fflags__h25872 =
(m_fflags_dummy2_0$Q_OUT && m_fflags_dummy2_1$Q_OUT) ?
m_fflags_rl :
5'd0 ;
@@ -1399,16 +1485,16 @@ module mkRobRowSynth(CLK,
end
always@(write_enq_x)
begin
case (write_enq_x[101:98])
case (write_enq_x[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 =
write_enq_x[101:98];
default: CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 = 4'd14;
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q5 =
write_enq_x[165:162];
default: CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q5 = 4'd14;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[101:98])
case (write_enq_x[165:162])
4'd0,
4'd1,
4'd2,
@@ -1422,9 +1508,9 @@ module mkRobRowSynth(CLK,
4'd11,
4'd12,
4'd13:
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 =
write_enq_x[101:98];
default: CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 = 4'd15;
CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q6 =
write_enq_x[165:162];
default: CASE_write_enq_x_BITS_165_TO_162_0_write_enq_x_ETC__q6 = 4'd15;
endcase
end
always@(write_enq_x)
@@ -1438,7 +1524,7 @@ module mkRobRowSynth(CLK,
end
always@(write_enq_x)
begin
case (write_enq_x[116:105])
case (write_enq_x[180:169])
12'd1,
12'd2,
12'd3,
@@ -1475,9 +1561,9 @@ module mkRobRowSynth(CLK,
12'd3858,
12'd3859,
12'd3860:
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 =
write_enq_x[116:105];
default: CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 =
CASE_write_enq_x_BITS_180_TO_169_1_write_enq_x_ETC__q8 =
write_enq_x[180:169];
default: CASE_write_enq_x_BITS_180_TO_169_1_write_enq_x_ETC__q8 =
12'd2303;
endcase
end
@@ -1497,6 +1583,7 @@ module mkRobRowSynth(CLK,
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
m_trap_rl <= `BSV_ASSIGNMENT_DELAY 6'h2A;
m_tval_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
end
else
begin
@@ -1521,6 +1608,7 @@ module mkRobRowSynth(CLK,
if (m_spec_bits_rl$EN)
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_rl$D_IN;
if (m_trap_rl$EN) m_trap_rl <= `BSV_ASSIGNMENT_DELAY m_trap_rl$D_IN;
if (m_tval_rl$EN) m_tval_rl <= `BSV_ASSIGNMENT_DELAY m_tval_rl$D_IN;
end
if (m_claimed_phy_reg$EN)
m_claimed_phy_reg <= `BSV_ASSIGNMENT_DELAY m_claimed_phy_reg$D_IN;
@@ -1529,6 +1617,7 @@ module mkRobRowSynth(CLK,
m_epochIncremented <= `BSV_ASSIGNMENT_DELAY m_epochIncremented$D_IN;
if (m_iType$EN) m_iType <= `BSV_ASSIGNMENT_DELAY m_iType$D_IN;
if (m_lsqTag$EN) m_lsqTag <= `BSV_ASSIGNMENT_DELAY m_lsqTag$D_IN;
if (m_orig_inst$EN) m_orig_inst <= `BSV_ASSIGNMENT_DELAY m_orig_inst$D_IN;
if (m_pc$EN) m_pc <= `BSV_ASSIGNMENT_DELAY m_pc$D_IN;
if (m_will_dirty_fpu_state$EN)
m_will_dirty_fpu_state <= `BSV_ASSIGNMENT_DELAY
@@ -1550,11 +1639,13 @@ module mkRobRowSynth(CLK,
m_lsqTag = 6'h2A;
m_memAccessAtCommit_rl = 1'h0;
m_nonMMIOStDone_rl = 1'h0;
m_orig_inst = 32'hAAAAAAAA;
m_pc = 64'hAAAAAAAAAAAAAAAA;
m_ppc_vaddr_csrData_rl = 66'h2AAAAAAAAAAAAAAAA;
m_rob_inst_state_rl = 1'h0;
m_spec_bits_rl = 12'hAAA;
m_trap_rl = 6'h2A;
m_tval_rl = 64'hAAAAAAAAAAAAAAAA;
m_will_dirty_fpu_state = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
@@ -1568,39 +1659,39 @@ module mkRobRowSynth(CLK,
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d655)
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d677)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d655)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 205, column 60\ncsr valid should match");
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d677)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 210, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d655)
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d677)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d663)
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d685)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d663)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 205, column 60\ncsr valid should match");
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d685)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 210, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_42_BIT_12_43_EQ_setExecuted_doFinish_ETC___d663)
NOT_m_csr_55_BIT_12_56_EQ_setExecuted_doFinish_ETC___d685)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524)
m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 312, column 52\ncannot have trap");
m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 322, column 52\ncannot have trap");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__19_AND_m_trap_dummy2_1_r_ETC___d524)
m_trap_dummy2_0_read__33_AND_m_trap_dummy2_1_r_ETC___d538)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
@@ -1611,7 +1702,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
setExecuted_doFinishMem_non_mmio_st_done)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 231, column 18\ncannot both be true");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 237, column 18\ncannot both be true");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
@@ -1626,7 +1717,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
m_iType != 5'd5)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 235, column 35\nmust be St");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 241, column 35\nmust be St");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
@@ -1637,7 +1728,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 277, column 40\nld killed must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 285, column 40\nld killed must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1645,7 +1736,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 278, column 48\nmem access at commit must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 286, column 48\nmem access at commit must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1653,7 +1744,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 279, column 42\nlsq notified must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 287, column 42\nlsq notified must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1661,7 +1752,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 280, column 36\nnon mmio st must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 288, column 36\nnon mmio st must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13]) $finish(32'd0);
end

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardAggr.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardAggr.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardCons.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkScoreboardCons.v
View File

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSimpleRespQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSimpleRespQ.v
View File

4
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Map.v
View File

@@ -267,13 +267,13 @@ module mkSoC_Map(CLK,
// value method m_is_mem_addr
assign m_is_mem_addr =
m_is_mem_addr_addr >= 64'h0000000000001000 &&
m_is_mem_addr_addr < 64'd8192 ||
m_is_mem_addr_addr >= 64'h0000000080000000 &&
m_is_mem_addr_addr < 64'h0000000090000000 ;
// value method m_is_IO_addr
assign m_is_IO_addr =
m_is_IO_addr_addr >= 64'h0000000000001000 &&
m_is_IO_addr_addr < 64'd8192 ||
m_is_IO_addr_addr >= 64'h0000000002000000 &&
m_is_IO_addr_addr < 64'd33603584 ||
m_is_IO_addr_addr >= 64'h000000000C000000 &&

2
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSoC_Top.v
View File

@@ -1470,7 +1470,7 @@ module mkSoC_Top(CLK,
assign corew$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ;
assign corew$cpu_imem_master_wready = fabric$v_from_masters_0_wready ;
assign corew$debug_external_interrupt_req_set_not_clear = 1'd0 ;
assign corew$set_htif_addrs_fromhost_addr = 64'd0 ;
assign corew$set_htif_addrs_fromhost_addr = 64'h0000000080001040 ;
assign corew$set_htif_addrs_tohost_addr = set_watch_tohost_tohost_addr ;
assign corew$set_verbosity_logdelay = set_verbosity_logdelay ;
assign corew$set_verbosity_verbosity = set_verbosity_verbosity ;

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSpecTagManager.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSpecTagManager.v
View File

120
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSplitLSQ.v
View File

@@ -17327,51 +17327,51 @@ module mkSplitLSQ(CLK,
_dfoo573,
_dfoo673,
_dfoo677,
_dfoo683,
_dfoo681,
_dfoo685,
_dfoo689,
_dfoo693,
_dfoo697,
_dfoo701,
_dfoo703,
_dfoo705,
_dfoo709,
_dfoo715,
_dfoo713,
_dfoo717,
_dfoo721,
_dfoo725,
_dfoo729,
_dfoo731,
_dfoo733,
_dfoo737,
_dfoo743,
_dfoo745,
_dfoo741,
_dfoo747,
_dfoo749,
_dfoo753,
_dfoo759,
_dfoo757,
_dfoo761,
_dfoo765,
_dfoo865,
_dfoo871,
_dfoo877,
_dfoo883,
_dfoo889,
_dfoo891,
_dfoo895,
_dfoo901,
_dfoo907,
_dfoo913,
_dfoo919,
_dfoo925,
_dfoo931,
_dfoo939,
_dfoo945,
_dfoo935,
_dfoo937,
_dfoo943,
_dfoo949,
_dfoo955,
_dfoo961,
_dfoo957,
_dfoo963,
_dfoo967,
_dfoo973,
_dfoo979,
_dfoo985,
_dfoo989,
_dfoo991,
_dfoo997,
_dfoo999,
issueLd_lsqTag_EQ_0_1827_AND_SEL_ARR_ld_valid__ETC___d23186,
issueLd_lsqTag_EQ_10_3153_AND_SEL_ARR_ld_valid_ETC___d23196,
issueLd_lsqTag_EQ_11_3155_AND_SEL_ARR_ld_valid_ETC___d23197,
@@ -31625,7 +31625,7 @@ module mkSplitLSQ(CLK,
EN_deqLd &&
ld_depLdQDeq_1_dummy2_0_read__1744_AND_ld_depL_ETC___d13707 &&
ld_depLdQDeq_1_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_1_lat_1$whas = EN_issueLd && _dfoo997 ;
assign ld_depLdQDeq_1_lat_1$whas = EN_issueLd && _dfoo999 ;
assign ld_depLdQDeq_2_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_2_dummy2_0_read__1828_AND_ld_depL_ETC___d13747 &&
@@ -31635,7 +31635,7 @@ module mkSplitLSQ(CLK,
EN_deqLd &&
ld_depLdQDeq_3_dummy2_0_read__1912_AND_ld_depL_ETC___d13787 &&
ld_depLdQDeq_3_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_3_lat_1$whas = EN_issueLd && _dfoo985 ;
assign ld_depLdQDeq_3_lat_1$whas = EN_issueLd && _dfoo989 ;
assign ld_depLdQDeq_4_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_4_dummy2_0_read__1996_AND_ld_depL_ETC___d13827 &&
@@ -31655,12 +31655,12 @@ module mkSplitLSQ(CLK,
EN_deqLd &&
ld_depLdQDeq_7_dummy2_0_read__2248_AND_ld_depL_ETC___d13947 &&
ld_depLdQDeq_7_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_7_lat_1$whas = EN_issueLd && _dfoo961 ;
assign ld_depLdQDeq_7_lat_1$whas = EN_issueLd && _dfoo963 ;
assign ld_depLdQDeq_8_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_8_dummy2_0_read__2332_AND_ld_depL_ETC___d13987 &&
ld_depLdQDeq_8_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_8_lat_1$whas = EN_issueLd && _dfoo955 ;
assign ld_depLdQDeq_8_lat_1$whas = EN_issueLd && _dfoo957 ;
assign ld_depLdQDeq_9_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_9_dummy2_0_read__2416_AND_ld_depL_ETC___d14027 &&
@@ -31670,17 +31670,17 @@ module mkSplitLSQ(CLK,
EN_deqLd &&
ld_depLdQDeq_10_dummy2_0_read__2500_AND_ld_dep_ETC___d14067 &&
ld_depLdQDeq_10_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_10_lat_1$whas = EN_issueLd && _dfoo945 ;
assign ld_depLdQDeq_10_lat_1$whas = EN_issueLd && _dfoo943 ;
assign ld_depLdQDeq_11_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_11_dummy2_0_read__2584_AND_ld_dep_ETC___d14107 &&
ld_depLdQDeq_11_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_11_lat_1$whas = EN_issueLd && _dfoo939 ;
assign ld_depLdQDeq_11_lat_1$whas = EN_issueLd && _dfoo937 ;
assign ld_depLdQDeq_12_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_12_dummy2_0_read__2668_AND_ld_dep_ETC___d14147 &&
ld_depLdQDeq_12_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_12_lat_1$whas = EN_issueLd && _dfoo931 ;
assign ld_depLdQDeq_12_lat_1$whas = EN_issueLd && _dfoo935 ;
assign ld_depLdQDeq_13_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_13_dummy2_0_read__2752_AND_ld_dep_ETC___d14187 &&
@@ -31715,7 +31715,7 @@ module mkSplitLSQ(CLK,
EN_deqLd &&
ld_depLdQDeq_19_dummy2_0_read__3256_AND_ld_dep_ETC___d14427 &&
ld_depLdQDeq_19_rl[4:0] == x__h1062868 ;
assign ld_depLdQDeq_19_lat_1$whas = EN_issueLd && _dfoo889 ;
assign ld_depLdQDeq_19_lat_1$whas = EN_issueLd && _dfoo891 ;
assign ld_depLdQDeq_20_lat_0$whas =
EN_deqLd &&
ld_depLdQDeq_20_dummy2_0_read__3340_AND_ld_dep_ETC___d14467 &&
@@ -31747,7 +31747,7 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_1_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_1_dummy2_1_read__1776_AND_ld_depS_ETC___d26275 ;
assign ld_depStQDeq_2_lat_0$whas = EN_issueLd && _dfoo759 ;
assign ld_depStQDeq_2_lat_0$whas = EN_issueLd && _dfoo757 ;
assign ld_depStQDeq_2_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_2_dummy2_1_read__1860_AND_ld_depS_ETC___d26285 ;
@@ -31759,11 +31759,11 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_4_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_4_dummy2_1_read__2028_AND_ld_depS_ETC___d26305 ;
assign ld_depStQDeq_5_lat_0$whas = EN_issueLd && _dfoo745 ;
assign ld_depStQDeq_5_lat_0$whas = EN_issueLd && _dfoo747 ;
assign ld_depStQDeq_5_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_5_dummy2_1_read__2112_AND_ld_depS_ETC___d26315 ;
assign ld_depStQDeq_6_lat_0$whas = EN_issueLd && _dfoo743 ;
assign ld_depStQDeq_6_lat_0$whas = EN_issueLd && _dfoo741 ;
assign ld_depStQDeq_6_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_6_dummy2_1_read__2196_AND_ld_depS_ETC___d26325 ;
@@ -31775,7 +31775,7 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_8_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_8_dummy2_1_read__2364_AND_ld_depS_ETC___d26345 ;
assign ld_depStQDeq_9_lat_0$whas = EN_issueLd && _dfoo729 ;
assign ld_depStQDeq_9_lat_0$whas = EN_issueLd && _dfoo731 ;
assign ld_depStQDeq_9_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_9_dummy2_1_read__2448_AND_ld_depS_ETC___d26355 ;
@@ -31791,7 +31791,7 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_12_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_12_dummy2_1_read__2700_AND_ld_dep_ETC___d26385 ;
assign ld_depStQDeq_13_lat_0$whas = EN_issueLd && _dfoo715 ;
assign ld_depStQDeq_13_lat_0$whas = EN_issueLd && _dfoo713 ;
assign ld_depStQDeq_13_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_13_dummy2_1_read__2784_AND_ld_dep_ETC___d26395 ;
@@ -31803,7 +31803,7 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_15_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_15_dummy2_1_read__2952_AND_ld_dep_ETC___d26415 ;
assign ld_depStQDeq_16_lat_0$whas = EN_issueLd && _dfoo701 ;
assign ld_depStQDeq_16_lat_0$whas = EN_issueLd && _dfoo703 ;
assign ld_depStQDeq_16_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_16_dummy2_1_read__3036_AND_ld_dep_ETC___d26425 ;
@@ -31823,7 +31823,7 @@ module mkSplitLSQ(CLK,
assign ld_depStQDeq_20_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_20_dummy2_1_read__3372_AND_ld_dep_ETC___d26465 ;
assign ld_depStQDeq_21_lat_0$whas = EN_issueLd && _dfoo683 ;
assign ld_depStQDeq_21_lat_0$whas = EN_issueLd && _dfoo681 ;
assign ld_depStQDeq_21_lat_1$whas =
EN_deqSt &&
ld_depStQDeq_21_dummy2_1_read__3456_AND_ld_dep_ETC___d26475 ;
@@ -38889,7 +38889,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_10_dummy2_1
assign ld_depLdQDeq_10_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_10_dummy2_1$EN = EN_issueLd && _dfoo945 ;
assign ld_depLdQDeq_10_dummy2_1$EN = EN_issueLd && _dfoo943 ;
// submodule ld_depLdQDeq_10_dummy2_2
assign ld_depLdQDeq_10_dummy2_2$D_IN = 1'd1 ;
@@ -38901,7 +38901,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_11_dummy2_1
assign ld_depLdQDeq_11_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_11_dummy2_1$EN = EN_issueLd && _dfoo939 ;
assign ld_depLdQDeq_11_dummy2_1$EN = EN_issueLd && _dfoo937 ;
// submodule ld_depLdQDeq_11_dummy2_2
assign ld_depLdQDeq_11_dummy2_2$D_IN = 1'd1 ;
@@ -38913,7 +38913,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_12_dummy2_1
assign ld_depLdQDeq_12_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_12_dummy2_1$EN = EN_issueLd && _dfoo931 ;
assign ld_depLdQDeq_12_dummy2_1$EN = EN_issueLd && _dfoo935 ;
// submodule ld_depLdQDeq_12_dummy2_2
assign ld_depLdQDeq_12_dummy2_2$D_IN = 1'd1 ;
@@ -38997,7 +38997,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_19_dummy2_1
assign ld_depLdQDeq_19_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_19_dummy2_1$EN = EN_issueLd && _dfoo889 ;
assign ld_depLdQDeq_19_dummy2_1$EN = EN_issueLd && _dfoo891 ;
// submodule ld_depLdQDeq_19_dummy2_2
assign ld_depLdQDeq_19_dummy2_2$D_IN = 1'd1 ;
@@ -39009,7 +39009,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_1_dummy2_1
assign ld_depLdQDeq_1_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_1_dummy2_1$EN = EN_issueLd && _dfoo997 ;
assign ld_depLdQDeq_1_dummy2_1$EN = EN_issueLd && _dfoo999 ;
// submodule ld_depLdQDeq_1_dummy2_2
assign ld_depLdQDeq_1_dummy2_2$D_IN = 1'd1 ;
@@ -39081,7 +39081,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_3_dummy2_1
assign ld_depLdQDeq_3_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_3_dummy2_1$EN = EN_issueLd && _dfoo985 ;
assign ld_depLdQDeq_3_dummy2_1$EN = EN_issueLd && _dfoo989 ;
// submodule ld_depLdQDeq_3_dummy2_2
assign ld_depLdQDeq_3_dummy2_2$D_IN = 1'd1 ;
@@ -39129,7 +39129,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_7_dummy2_1
assign ld_depLdQDeq_7_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_7_dummy2_1$EN = EN_issueLd && _dfoo961 ;
assign ld_depLdQDeq_7_dummy2_1$EN = EN_issueLd && _dfoo963 ;
// submodule ld_depLdQDeq_7_dummy2_2
assign ld_depLdQDeq_7_dummy2_2$D_IN = 1'd1 ;
@@ -39141,7 +39141,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depLdQDeq_8_dummy2_1
assign ld_depLdQDeq_8_dummy2_1$D_IN = 1'd1 ;
assign ld_depLdQDeq_8_dummy2_1$EN = EN_issueLd && _dfoo955 ;
assign ld_depLdQDeq_8_dummy2_1$EN = EN_issueLd && _dfoo957 ;
// submodule ld_depLdQDeq_8_dummy2_2
assign ld_depLdQDeq_8_dummy2_2$D_IN = 1'd1 ;
@@ -39497,7 +39497,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_13_dummy2_0
assign ld_depStQDeq_13_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_13_dummy2_0$EN = EN_issueLd && _dfoo715 ;
assign ld_depStQDeq_13_dummy2_0$EN = EN_issueLd && _dfoo713 ;
// submodule ld_depStQDeq_13_dummy2_1
assign ld_depStQDeq_13_dummy2_1$D_IN = 1'd1 ;
@@ -39533,7 +39533,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_16_dummy2_0
assign ld_depStQDeq_16_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_16_dummy2_0$EN = EN_issueLd && _dfoo701 ;
assign ld_depStQDeq_16_dummy2_0$EN = EN_issueLd && _dfoo703 ;
// submodule ld_depStQDeq_16_dummy2_1
assign ld_depStQDeq_16_dummy2_1$D_IN = 1'd1 ;
@@ -39605,7 +39605,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_21_dummy2_0
assign ld_depStQDeq_21_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_21_dummy2_0$EN = EN_issueLd && _dfoo683 ;
assign ld_depStQDeq_21_dummy2_0$EN = EN_issueLd && _dfoo681 ;
// submodule ld_depStQDeq_21_dummy2_1
assign ld_depStQDeq_21_dummy2_1$D_IN = 1'd1 ;
@@ -39641,7 +39641,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_2_dummy2_0
assign ld_depStQDeq_2_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_2_dummy2_0$EN = EN_issueLd && _dfoo759 ;
assign ld_depStQDeq_2_dummy2_0$EN = EN_issueLd && _dfoo757 ;
// submodule ld_depStQDeq_2_dummy2_1
assign ld_depStQDeq_2_dummy2_1$D_IN = 1'd1 ;
@@ -39677,7 +39677,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_5_dummy2_0
assign ld_depStQDeq_5_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_5_dummy2_0$EN = EN_issueLd && _dfoo745 ;
assign ld_depStQDeq_5_dummy2_0$EN = EN_issueLd && _dfoo747 ;
// submodule ld_depStQDeq_5_dummy2_1
assign ld_depStQDeq_5_dummy2_1$D_IN = 1'd1 ;
@@ -39689,7 +39689,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_6_dummy2_0
assign ld_depStQDeq_6_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_6_dummy2_0$EN = EN_issueLd && _dfoo743 ;
assign ld_depStQDeq_6_dummy2_0$EN = EN_issueLd && _dfoo741 ;
// submodule ld_depStQDeq_6_dummy2_1
assign ld_depStQDeq_6_dummy2_1$D_IN = 1'd1 ;
@@ -39725,7 +39725,7 @@ module mkSplitLSQ(CLK,
// submodule ld_depStQDeq_9_dummy2_0
assign ld_depStQDeq_9_dummy2_0$D_IN = 1'd1 ;
assign ld_depStQDeq_9_dummy2_0$EN = EN_issueLd && _dfoo729 ;
assign ld_depStQDeq_9_dummy2_0$EN = EN_issueLd && _dfoo731 ;
// submodule ld_depStQDeq_9_dummy2_1
assign ld_depStQDeq_9_dummy2_1$D_IN = 1'd1 ;
@@ -56417,7 +56417,7 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo683 =
assign _dfoo681 =
issueLd_lsqTag == 5'd21 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56442,7 +56442,7 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo701 =
assign _dfoo703 =
issueLd_lsqTag == 5'd16 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56457,7 +56457,7 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo715 =
assign _dfoo713 =
issueLd_lsqTag == 5'd13 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56477,7 +56477,7 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo729 =
assign _dfoo731 =
issueLd_lsqTag == 5'd9 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56492,12 +56492,12 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo743 =
assign _dfoo741 =
issueLd_lsqTag == 5'd6 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo745 =
assign _dfoo747 =
issueLd_lsqTag == 5'd5 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56512,7 +56512,7 @@ module mkSplitLSQ(CLK,
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
SEL_ARR_st_valid_0_dummy2_0_read__7443_AND_st__ETC___d23343) ;
assign _dfoo759 =
assign _dfoo757 =
issueLd_lsqTag == 5'd2 &&
(NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23261 ||
NOT_SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_ETC___d23248 &&
@@ -56547,7 +56547,7 @@ module mkSplitLSQ(CLK,
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo889 =
assign _dfoo891 =
issueLd_lsqTag == 5'd19 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
@@ -56582,17 +56582,17 @@ module mkSplitLSQ(CLK,
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo931 =
assign _dfoo935 =
issueLd_lsqTag == 5'd12 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo939 =
assign _dfoo937 =
issueLd_lsqTag == 5'd11 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo945 =
assign _dfoo943 =
issueLd_lsqTag == 5'd10 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
@@ -56602,12 +56602,12 @@ module mkSplitLSQ(CLK,
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo955 =
assign _dfoo957 =
issueLd_lsqTag == 5'd8 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo961 =
assign _dfoo963 =
issueLd_lsqTag == 5'd7 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
@@ -56627,7 +56627,7 @@ module mkSplitLSQ(CLK,
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo985 =
assign _dfoo989 =
issueLd_lsqTag == 5'd3 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
@@ -56637,7 +56637,7 @@ module mkSplitLSQ(CLK,
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||
SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23214) ;
assign _dfoo997 =
assign _dfoo999 =
issueLd_lsqTag == 5'd1 &&
(SEL_ARR_ld_valid_0_dummy2_1_read__1630_AND_IF__ETC___d23129 &&
SEL_ARR_ld_acq_0_1831_ld_acq_1_1835_ld_acq_2_1_ETC___d23131 ||

72
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSplitTransCache.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSplitTransCache.v
View File

@@ -945,8 +945,8 @@ module mkSplitTransCache(CLK,
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2,
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1,
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2;
wire MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2,
MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1,
wire MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1,
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1,
MUX_caches_0_validVec_0$write_1__SEL_1,
MUX_caches_0_validVec_1$write_1__SEL_1,
MUX_caches_0_validVec_10$write_1__SEL_1,
@@ -971,8 +971,8 @@ module mkSplitTransCache(CLK,
MUX_caches_0_validVec_7$write_1__SEL_1,
MUX_caches_0_validVec_8$write_1__SEL_1,
MUX_caches_0_validVec_9$write_1__SEL_1,
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2,
MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1,
MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1,
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1,
MUX_caches_1_validVec_0$write_1__SEL_1,
MUX_caches_1_validVec_1$write_1__SEL_1,
MUX_caches_1_validVec_10$write_1__SEL_1,
@@ -1625,7 +1625,9 @@ module mkSplitTransCache(CLK,
assign WILL_FIRE_RL_respQ_full_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1 = EN_addEntry && _dfoo7 ;
assign MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1 =
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
assign MUX_caches_0_validVec_0$write_1__SEL_1 =
EN_addEntry && v__h56470 == 5'd0 &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d1067 &&
@@ -1722,7 +1724,9 @@ module mkSplitTransCache(CLK,
EN_addEntry && v__h56470 == 5'd9 &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d1067 &&
x__h46068 == 2'd0 ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1 = EN_addEntry && _dfoo1 ;
assign MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1 =
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
assign MUX_caches_1_validVec_0$write_1__SEL_1 =
EN_addEntry && v__h75650 == 5'd0 &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1504 &&
@@ -1821,44 +1825,44 @@ module mkSplitTransCache(CLK,
x__h46068 == 2'd1 ;
assign MUX_caches_0_lruBit_lat_0$wset_1__VAL_1 =
(val__h8225 == 24'd16777215) ? x__h8299 : val__h8225 ;
assign MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 =
assign MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_caches_0_doUpdateRep || EN_flush ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 =
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, i__h28125 } ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 =
(IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d914 &&
x__h46068 == 2'd0) ?
{ 1'd1,
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_addEnt_ETC___d940 } :
{ 1'd1, v__h56470 } ;
assign MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, i__h28125 } ;
assign MUX_caches_1_lruBit_lat_0$wset_1__VAL_1 =
(val__h16766 == 24'd16777215) ? x__h16840 : val__h16766 ;
assign MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 =
assign MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 =
WILL_FIRE_RL_caches_1_doUpdateRep || EN_flush ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 =
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, i__h37542 } ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 =
(IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1352 &&
x__h46068 == 2'd1) ?
{ 1'd1,
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_addEnt_ETC___d1377 } :
{ 1'd1, v__h75650 } ;
assign MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, i__h37542 } ;
// inlined wires
assign caches_0_updRepIdx_lat_1$wget =
MUX_caches_0_updRepIdx_lat_1$wset_1__SEL_1 ?
MUX_caches_0_updRepIdx_dummy2_1$write_1__SEL_1 ?
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_1 :
MUX_caches_0_updRepIdx_lat_1$wset_1__VAL_2 ;
assign caches_0_updRepIdx_lat_1$whas =
EN_addEntry && _dfoo7 ||
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ||
EN_addEntry && _dfoo7 ;
assign caches_1_updRepIdx_lat_1$wget =
MUX_caches_1_updRepIdx_lat_1$wset_1__SEL_1 ?
MUX_caches_1_updRepIdx_dummy2_1$write_1__SEL_1 ?
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_1 :
MUX_caches_1_updRepIdx_lat_1$wset_1__VAL_2 ;
assign caches_1_updRepIdx_lat_1$whas =
EN_addEntry && _dfoo1 ||
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ||
EN_addEntry && _dfoo1 ;
// register caches_0_lruBit_rl
assign caches_0_lruBit_rl$D_IN =
@@ -2679,7 +2683,7 @@ module mkSplitTransCache(CLK,
// submodule caches_0_lruBit_dummy2_0
assign caches_0_lruBit_dummy2_0$D_IN = 1'd1 ;
assign caches_0_lruBit_dummy2_0$EN =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_0_lruBit_dummy2_1
assign caches_0_lruBit_dummy2_1$D_IN = 1'b0 ;
@@ -2688,19 +2692,19 @@ module mkSplitTransCache(CLK,
// submodule caches_0_updRepIdx_dummy2_0
assign caches_0_updRepIdx_dummy2_0$D_IN = 1'd1 ;
assign caches_0_updRepIdx_dummy2_0$EN =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_0_updRepIdx_dummy2_1
assign caches_0_updRepIdx_dummy2_1$D_IN = 1'd1 ;
assign caches_0_updRepIdx_dummy2_1$EN =
EN_addEntry && _dfoo7 ||
EN_req &&
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ;
IF_NOT_caches_0_validVec_0_14_15_OR_NOT_req_vp_ETC___d347 ||
EN_addEntry && _dfoo7 ;
// submodule caches_1_lruBit_dummy2_0
assign caches_1_lruBit_dummy2_0$D_IN = 1'd1 ;
assign caches_1_lruBit_dummy2_0$EN =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_1_lruBit_dummy2_1
assign caches_1_lruBit_dummy2_1$D_IN = 1'b0 ;
@@ -2709,14 +2713,14 @@ module mkSplitTransCache(CLK,
// submodule caches_1_updRepIdx_dummy2_0
assign caches_1_updRepIdx_dummy2_0$D_IN = 1'd1 ;
assign caches_1_updRepIdx_dummy2_0$EN =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ;
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
// submodule caches_1_updRepIdx_dummy2_1
assign caches_1_updRepIdx_dummy2_1$D_IN = 1'd1 ;
assign caches_1_updRepIdx_dummy2_1$EN =
EN_addEntry && _dfoo1 ||
EN_req &&
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ;
IF_NOT_caches_1_validVec_0_72_73_OR_NOT_req_vp_ETC___d605 ||
EN_addEntry && _dfoo1 ;
// submodule respQ_deqP_dummy2_0
assign respQ_deqP_dummy2_0$D_IN = 1'd1 ;
@@ -3960,18 +3964,18 @@ module mkSplitTransCache(CLK,
~IF_caches_0_lruBit_lat_0_whas_THEN_caches_0_lr_ETC___d6 :
24'd16777215 ;
assign IF_caches_0_lruBit_lat_0_whas_THEN_caches_0_lr_ETC___d6 =
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
upd__h60756 :
caches_0_lruBit_rl ;
assign IF_caches_0_updRepIdx_lat_1_whas_THEN_caches_0_ETC___d17 =
caches_0_updRepIdx_lat_1$whas ?
caches_0_updRepIdx_lat_1$wget[5] :
!MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 &&
!MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
caches_0_updRepIdx_rl[5] ;
assign IF_caches_0_updRepIdx_lat_1_whas_THEN_caches_0_ETC___d27 =
caches_0_updRepIdx_lat_1$whas ?
caches_0_updRepIdx_lat_1$wget[4:0] :
(MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
(MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
5'b01010 :
caches_0_updRepIdx_rl[4:0]) ;
assign IF_caches_0_validVec_0_14_AND_caches_0_validVe_ETC___d1112 =
@@ -4021,18 +4025,18 @@ module mkSplitTransCache(CLK,
~IF_caches_1_lruBit_lat_0_whas__0_THEN_caches_1_ETC___d53 :
24'd16777215 ;
assign IF_caches_1_lruBit_lat_0_whas__0_THEN_caches_1_ETC___d53 =
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
upd__h79933 :
caches_1_lruBit_rl ;
assign IF_caches_1_updRepIdx_lat_1_whas__5_THEN_cache_ETC___d64 =
caches_1_updRepIdx_lat_1$whas ?
caches_1_updRepIdx_lat_1$wget[5] :
!MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 &&
!MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
caches_1_updRepIdx_rl[5] ;
assign IF_caches_1_updRepIdx_lat_1_whas__5_THEN_cache_ETC___d74 =
caches_1_updRepIdx_lat_1$whas ?
caches_1_updRepIdx_lat_1$wget[4:0] :
(MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ?
(MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
5'b01010 :
caches_1_updRepIdx_rl[4:0]) ;
assign IF_caches_1_validVec_0_72_AND_caches_1_validVe_ETC___d1549 =
@@ -4079,7 +4083,7 @@ module mkSplitTransCache(CLK,
IF_caches_1_validVec_8_36_AND_caches_1_validVe_ETC___d1542 ;
assign NOT_caches_0_updRepIdx_dummy2_1_read__3_48_OR__ETC___d749 =
!caches_0_updRepIdx_dummy2_1$Q_OUT ||
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_2 ||
MUX_caches_0_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
!caches_0_updRepIdx_rl[5] ;
assign NOT_caches_0_validVec_0_14_15_OR_NOT_addEntry__ETC___d783 =
(!caches_0_validVec_0 ||
@@ -4239,7 +4243,7 @@ module mkSplitTransCache(CLK,
!caches_0_validVec_15 ;
assign NOT_caches_1_updRepIdx_dummy2_1_read__0_51_OR__ETC___d752 =
!caches_1_updRepIdx_dummy2_1$Q_OUT ||
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_2 ||
MUX_caches_1_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
!caches_1_updRepIdx_rl[5] ;
assign NOT_caches_1_validVec_0_72_73_OR_NOT_addEntry__ETC___d1221 =
(!caches_1_validVec_0 ||

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkStoreBufferEhr.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkStoreBufferEhr.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSyncBramFifo_w36_d512.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSyncBramFifo_w36_d512.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkSyncFifo_w32_d16.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkSyncFifo_w32_d16.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTop_HW_Side.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkTourGHistReg.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourGHistReg.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkTourPred.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourPred.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkTourPredSecure.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkTourPredSecure.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkUART.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDiv.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDiv.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivIP.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivIP.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivSim.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpDivSim.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFma.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFma.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaIP.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaIP.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaSim.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpFmaSim.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrt.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrt.v
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builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtIP.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtIP.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtSim.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkXilinxFpSqrtSim.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_alu.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_alu.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_aluBr.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_aluBr.v
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0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_amoExec.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_amoExec.v
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94
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_basicExec.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_basicExec.v
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@@ -12,13 +12,15 @@
// basicExec_rVal2 I 64
// basicExec_pc I 64
// basicExec_ppc I 64
// basicExec_orig_inst I 32
//
// Combinational paths from inputs to outputs:
// (basicExec_dInst,
// basicExec_rVal1,
// basicExec_rVal2,
// basicExec_pc,
// basicExec_ppc) -> basicExec
// basicExec_ppc,
// basicExec_orig_inst) -> basicExec
//
//
@@ -40,6 +42,7 @@ module module_basicExec(basicExec_dInst,
basicExec_rVal2,
basicExec_pc,
basicExec_ppc,
basicExec_orig_inst,
basicExec);
// value method basicExec
input [71 : 0] basicExec_dInst;
@@ -47,84 +50,91 @@ module module_basicExec(basicExec_dInst,
input [63 : 0] basicExec_rVal2;
input [63 : 0] basicExec_pc;
input [63 : 0] basicExec_ppc;
input [31 : 0] basicExec_orig_inst;
output [321 : 0] basicExec;
// signals for module outputs
wire [321 : 0] basicExec;
// remaining internal signals
reg [63 : 0] x__h23, x__h263;
wire [193 : 0] IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43;
wire [63 : 0] SEXT_basicExec_dInst_BITS_31_TO_0_3___d14,
aluVal2__h33,
alu_result__h35,
basicExec_pc_PLUS_4___d10,
cf_nextPc__h294;
reg [63 : 0] x__h24, x__h302;
wire [193 : 0] IF_basicExec_dInst_BITS_71_TO_67_EQ_4_1_OR_bas_ETC___d46;
wire [63 : 0] SEXT_basicExec_dInst_BITS_31_TO_0_6___d17,
aluVal2__h34,
alu_result__h36,
basicExec_pc_PLUS_IF_basicExec_orig_inst_BITS__ETC___d13,
cf_nextPc__h333,
fallthrough_incr__h41;
wire [31 : 0] basicExec_dInst_BITS_31_TO_0__q1;
wire aluBr___d37;
wire aluBr___d40;
// value method basicExec
assign basicExec =
{ x__h23,
alu_result__h35,
IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43 } ;
{ x__h24,
alu_result__h36,
IF_basicExec_dInst_BITS_71_TO_67_EQ_4_1_OR_bas_ETC___d46 } ;
// remaining internal signals
module_alu instance_alu_1(.alu_a(basicExec_rVal1),
.alu_b(aluVal2__h33),
.alu_b(aluVal2__h34),
.alu_func((basicExec_dInst[66:64] == 3'd0) ?
basicExec_dInst[50:46] :
5'd0),
.alu(alu_result__h35));
.alu(alu_result__h36));
module_aluBr instance_aluBr_0(.aluBr_a(basicExec_rVal1),
.aluBr_b(basicExec_rVal2),
.aluBr_brFunc((basicExec_dInst[66:64] ==
3'd1) ?
basicExec_dInst[48:46] :
3'd7),
.aluBr(aluBr___d37));
.aluBr(aluBr___d40));
module_brAddrCalc instance_brAddrCalc_2(.brAddrCalc_pc(basicExec_pc),
.brAddrCalc_val(basicExec_rVal1),
.brAddrCalc_iType(basicExec_dInst[71:67]),
.brAddrCalc_imm(SEXT_basicExec_dInst_BITS_31_TO_0_3___d14),
.brAddrCalc_taken(aluBr___d37),
.brAddrCalc(cf_nextPc__h294));
assign IF_basicExec_dInst_BITS_71_TO_67_EQ_4_8_OR_bas_ETC___d43 =
{ x__h263,
.brAddrCalc_imm(SEXT_basicExec_dInst_BITS_31_TO_0_6___d17),
.brAddrCalc_taken(aluBr___d40),
.brAddrCalc_orig_inst(basicExec_orig_inst),
.brAddrCalc(cf_nextPc__h333));
assign IF_basicExec_dInst_BITS_71_TO_67_EQ_4_1_OR_bas_ETC___d46 =
{ x__h302,
basicExec_pc,
cf_nextPc__h294,
aluBr___d37,
cf_nextPc__h294 != basicExec_ppc } ;
assign SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 =
cf_nextPc__h333,
aluBr___d40,
cf_nextPc__h333 != basicExec_ppc } ;
assign SEXT_basicExec_dInst_BITS_31_TO_0_6___d17 =
{ {32{basicExec_dInst_BITS_31_TO_0__q1[31]}},
basicExec_dInst_BITS_31_TO_0__q1 } ;
assign aluVal2__h33 =
assign aluVal2__h34 =
basicExec_dInst[32] ?
SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 :
SEXT_basicExec_dInst_BITS_31_TO_0_6___d17 :
basicExec_rVal2 ;
assign basicExec_dInst_BITS_31_TO_0__q1 = basicExec_dInst[31:0] ;
assign basicExec_pc_PLUS_4___d10 = basicExec_pc + 64'd4 ;
always@(basicExec_dInst or
alu_result__h35 or
basicExec_rVal2 or
basicExec_pc_PLUS_4___d10 or
basicExec_pc or
SEXT_basicExec_dInst_BITS_31_TO_0_3___d14 or basicExec_rVal1)
assign basicExec_pc_PLUS_IF_basicExec_orig_inst_BITS__ETC___d13 =
basicExec_pc + fallthrough_incr__h41 ;
assign fallthrough_incr__h41 =
(basicExec_orig_inst[1:0] == 2'b11) ? 64'd4 : 64'd2 ;
always@(basicExec_dInst or cf_nextPc__h333 or alu_result__h36)
begin
case (basicExec_dInst[71:67])
5'd2, 5'd5, 5'd7: x__h23 = basicExec_rVal2;
5'd8, 5'd9: x__h23 = basicExec_pc_PLUS_4___d10;
5'd11:
x__h23 = basicExec_pc + SEXT_basicExec_dInst_BITS_31_TO_0_3___d14;
5'd13: x__h23 = basicExec_rVal1;
default: x__h23 = alu_result__h35;
5'd2, 5'd4, 5'd5, 5'd6, 5'd7: x__h302 = alu_result__h36;
default: x__h302 = cf_nextPc__h333;
endcase
end
always@(basicExec_dInst or cf_nextPc__h294 or alu_result__h35)
always@(basicExec_dInst or
alu_result__h36 or
basicExec_rVal2 or
basicExec_pc_PLUS_IF_basicExec_orig_inst_BITS__ETC___d13 or
basicExec_pc or
SEXT_basicExec_dInst_BITS_31_TO_0_6___d17 or basicExec_rVal1)
begin
case (basicExec_dInst[71:67])
5'd2, 5'd4, 5'd5, 5'd6, 5'd7: x__h263 = alu_result__h35;
default: x__h263 = cf_nextPc__h294;
5'd2, 5'd5, 5'd7: x__h24 = basicExec_rVal2;
5'd8, 5'd9:
x__h24 = basicExec_pc_PLUS_IF_basicExec_orig_inst_BITS__ETC___d13;
5'd11:
x__h24 = basicExec_pc + SEXT_basicExec_dInst_BITS_31_TO_0_6___d17;
5'd13: x__h24 = basicExec_rVal1;
default: x__h24 = alu_result__h36;
endcase
end
endmodule // module_basicExec

19
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_brAddrCalc.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_brAddrCalc.v
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@@ -12,13 +12,15 @@
// brAddrCalc_iType I 5
// brAddrCalc_imm I 64
// brAddrCalc_taken I 1
// brAddrCalc_orig_inst I 32
//
// Combinational paths from inputs to outputs:
// (brAddrCalc_pc,
// brAddrCalc_val,
// brAddrCalc_iType,
// brAddrCalc_imm,
// brAddrCalc_taken) -> brAddrCalc
// brAddrCalc_taken,
// brAddrCalc_orig_inst) -> brAddrCalc
//
//
@@ -40,6 +42,7 @@ module module_brAddrCalc(brAddrCalc_pc,
brAddrCalc_iType,
brAddrCalc_imm,
brAddrCalc_taken,
brAddrCalc_orig_inst,
brAddrCalc);
// value method brAddrCalc
input [63 : 0] brAddrCalc_pc;
@@ -47,6 +50,7 @@ module module_brAddrCalc(brAddrCalc_pc,
input [4 : 0] brAddrCalc_iType;
input [63 : 0] brAddrCalc_imm;
input brAddrCalc_taken;
input [31 : 0] brAddrCalc_orig_inst;
output [63 : 0] brAddrCalc;
// signals for module outputs
@@ -55,11 +59,12 @@ module module_brAddrCalc(brAddrCalc_pc,
// remaining internal signals
wire [63 : 0] brAddrCalc_pc_PLUS_brAddrCalc_imm___d2,
brAddrCalc_val_PLUS_brAddrCalc_imm__q1,
pcPlus4__h27;
fallthrough_incr__h28,
pcPlusN__h29;
// value method brAddrCalc
always@(brAddrCalc_iType or
pcPlus4__h27 or
pcPlusN__h29 or
brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 or
brAddrCalc_val_PLUS_brAddrCalc_imm__q1 or brAddrCalc_taken)
begin
@@ -71,8 +76,8 @@ module module_brAddrCalc(brAddrCalc_pc,
brAddrCalc =
brAddrCalc_taken ?
brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 :
pcPlus4__h27;
default: brAddrCalc = pcPlus4__h27;
pcPlusN__h29;
default: brAddrCalc = pcPlusN__h29;
endcase
end
@@ -81,6 +86,8 @@ module module_brAddrCalc(brAddrCalc_pc,
brAddrCalc_pc + brAddrCalc_imm ;
assign brAddrCalc_val_PLUS_brAddrCalc_imm__q1 =
brAddrCalc_val + brAddrCalc_imm ;
assign pcPlus4__h27 = brAddrCalc_pc + 64'd4 ;
assign fallthrough_incr__h28 =
(brAddrCalc_orig_inst[1:0] == 2'b11) ? 64'd4 : 64'd2 ;
assign pcPlusN__h29 = brAddrCalc_pc + fallthrough_incr__h28 ;
endmodule // module_brAddrCalc

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_checkForException.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_checkForException.v
View File

18
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_decode.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_decode.v
View File

@@ -85,10 +85,10 @@ module module_decode(decode_inst,
wire [31 : 0] immB__h34, immI__h32, immJ__h36, immS__h33, immU__h35;
wire [20 : 0] IF_NOT_decode_inst_BITS_6_TO_0_EQ_51_39_AND_NO_ETC___d406,
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d408,
x__h10143;
x__h10144;
wire [14 : 0] IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d328;
wire [12 : 0] x__h10231;
wire [11 : 0] decode_inst_BITS_31_TO_20__q1, x__h10318;
wire [12 : 0] x__h10232;
wire [11 : 0] decode_inst_BITS_31_TO_20__q1, x__h10319;
wire [4 : 0] IF_NOT_decode_inst_BITS_26_TO_25_4_EQ_0b0_5_6__ETC___d30,
IF_SEXT_decode_inst_BITS_31_TO_20_7_8_BIT_10_0_ETC___d103;
wire decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46,
@@ -293,26 +293,26 @@ module module_decode(decode_inst,
decode_inst[23] | decode_inst[21] ;
assign decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49 =
decode_inst[26] | decode_inst[24] ;
assign immB__h34 = { {19{x__h10231[12]}}, x__h10231 } ;
assign immB__h34 = { {19{x__h10232[12]}}, x__h10232 } ;
assign immI__h32 =
{ {20{decode_inst_BITS_31_TO_20__q1[11]}},
decode_inst_BITS_31_TO_20__q1 } ;
assign immJ__h36 = { {11{x__h10143[20]}}, x__h10143 } ;
assign immS__h33 = { {20{x__h10318[11]}}, x__h10318 } ;
assign immJ__h36 = { {11{x__h10144[20]}}, x__h10144 } ;
assign immS__h33 = { {20{x__h10319[11]}}, x__h10319 } ;
assign immU__h35 = { decode_inst[31:12], 12'b0 } ;
assign x__h10143 =
assign x__h10144 =
{ decode_inst[31],
decode_inst[19:12],
decode_inst[20],
decode_inst[30:21],
1'b0 } ;
assign x__h10231 =
assign x__h10232 =
{ decode_inst[31],
decode_inst[7],
decode_inst[30:25],
decode_inst[11:8],
1'b0 } ;
assign x__h10318 = { decode_inst[31:25], decode_inst[11:7] } ;
assign x__h10319 = { decode_inst[31:25], decode_inst[11:7] } ;
always@(decode_inst or
decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 or
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49)

23
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_decodeBrPred.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_decodeBrPred.v
View File

@@ -10,11 +10,13 @@
// decodeBrPred_pc I 64
// decodeBrPred_dInst I 72
// decodeBrPred_histTaken I 1
// decodeBrPred_is_32b_inst I 1
//
// Combinational paths from inputs to outputs:
// (decodeBrPred_pc,
// decodeBrPred_dInst,
// decodeBrPred_histTaken) -> decodeBrPred
// decodeBrPred_histTaken,
// decodeBrPred_is_32b_inst) -> decodeBrPred
//
//
@@ -34,11 +36,13 @@
module module_decodeBrPred(decodeBrPred_pc,
decodeBrPred_dInst,
decodeBrPred_histTaken,
decodeBrPred_is_32b_inst,
decodeBrPred);
// value method decodeBrPred
input [63 : 0] decodeBrPred_pc;
input [71 : 0] decodeBrPred_dInst;
input decodeBrPred_histTaken;
input decodeBrPred_is_32b_inst;
output [64 : 0] decodeBrPred;
// signals for module outputs
@@ -46,7 +50,7 @@ module module_decodeBrPred(decodeBrPred_pc,
// remaining internal signals
reg [63 : 0] CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2;
wire [63 : 0] imm_val__h23, jTarget__h43, pcPlus4__h22;
wire [63 : 0] imm_val__h25, jTarget__h45, pcPlusN__h24;
wire [31 : 0] decodeBrPred_dInst_BITS_31_TO_0__q1;
// value method decodeBrPred
@@ -56,23 +60,24 @@ module module_decodeBrPred(decodeBrPred_pc,
// remaining internal signals
assign decodeBrPred_dInst_BITS_31_TO_0__q1 = decodeBrPred_dInst[31:0] ;
assign imm_val__h23 =
assign imm_val__h25 =
{ {32{decodeBrPred_dInst_BITS_31_TO_0__q1[31]}},
decodeBrPred_dInst_BITS_31_TO_0__q1 } ;
assign jTarget__h43 = decodeBrPred_pc + imm_val__h23 ;
assign pcPlus4__h22 = decodeBrPred_pc + 64'd4 ;
assign jTarget__h45 = decodeBrPred_pc + imm_val__h25 ;
assign pcPlusN__h24 =
decodeBrPred_pc + (decodeBrPred_is_32b_inst ? 64'd4 : 64'd2) ;
always@(decodeBrPred_dInst or
pcPlus4__h22 or jTarget__h43 or decodeBrPred_histTaken)
pcPlusN__h24 or jTarget__h45 or decodeBrPred_histTaken)
begin
case (decodeBrPred_dInst[71:67])
5'd8:
CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
jTarget__h43;
jTarget__h45;
5'd10:
CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
decodeBrPred_histTaken ? jTarget__h43 : pcPlus4__h22;
decodeBrPred_histTaken ? jTarget__h45 : pcPlusN__h24;
default: CASE_decodeBrPred_dInst_BITS_71_TO_67_8_jTarge_ETC__q2 =
pcPlus4__h22;
pcPlusN__h24;
endcase
end
endmodule // module_decodeBrPred

0
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_execFpuSimple.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_execFpuSimple.v
View File

23
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/module_getControlFlow.v → builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/module_getControlFlow.v
View File

@@ -12,13 +12,15 @@
// getControlFlow_rVal2 I 64
// getControlFlow_pc I 64
// getControlFlow_ppc I 64
// getControlFlow_orig_inst I 32
//
// Combinational paths from inputs to outputs:
// (getControlFlow_dInst,
// getControlFlow_rVal1,
// getControlFlow_rVal2,
// getControlFlow_pc,
// getControlFlow_ppc) -> getControlFlow
// getControlFlow_ppc,
// getControlFlow_orig_inst) -> getControlFlow
//
//
@@ -40,6 +42,7 @@ module module_getControlFlow(getControlFlow_dInst,
getControlFlow_rVal2,
getControlFlow_pc,
getControlFlow_ppc,
getControlFlow_orig_inst,
getControlFlow);
// value method getControlFlow
input [71 : 0] getControlFlow_dInst;
@@ -47,22 +50,23 @@ module module_getControlFlow(getControlFlow_dInst,
input [63 : 0] getControlFlow_rVal2;
input [63 : 0] getControlFlow_pc;
input [63 : 0] getControlFlow_ppc;
input [31 : 0] getControlFlow_orig_inst;
output [129 : 0] getControlFlow;
// signals for module outputs
wire [129 : 0] getControlFlow;
// remaining internal signals
wire [63 : 0] x__h50;
wire [31 : 0] x__h114;
wire [63 : 0] x__h51;
wire [31 : 0] x__h115;
wire aluBr___d9;
// value method getControlFlow
assign getControlFlow =
{ getControlFlow_pc,
x__h50,
x__h51,
getControlFlow_dInst[66:64] == 3'd1 && aluBr___d9,
x__h50 != getControlFlow_ppc } ;
x__h51 != getControlFlow_ppc } ;
// remaining internal signals
module_aluBr instance_aluBr_0(.aluBr_a(getControlFlow_rVal1),
@@ -72,12 +76,13 @@ module module_getControlFlow(getControlFlow_dInst,
module_brAddrCalc instance_brAddrCalc_1(.brAddrCalc_pc(getControlFlow_pc),
.brAddrCalc_val(getControlFlow_rVal1),
.brAddrCalc_iType(getControlFlow_dInst[71:67]),
.brAddrCalc_imm({ {32{x__h114[31]}},
x__h114 }),
.brAddrCalc_imm({ {32{x__h115[31]}},
x__h115 }),
.brAddrCalc_taken(getControlFlow_dInst[66:64] ==
3'd1 &&
aluBr___d9),
.brAddrCalc(x__h50));
assign x__h114 = getControlFlow_dInst[31:0] ;
.brAddrCalc_orig_inst(getControlFlow_orig_inst),
.brAddrCalc(x__h51));
assign x__h115 = getControlFlow_dInst[31:0] ;
endmodule // module_getControlFlow

1130
src_Core/CPU/CPU_Decode_C.bsv Normal file
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