No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
