Cheri-research/Toooba
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Changes needed to build for FPGA.

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This commit is contained in:
Jonathan Woodruff
2020-10-22 15:21:47 +01:00
parent bf77ac74ba
commit 69c697daf7
3 changed files with 22 additions and 2 deletions
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2
src_Core/CPU/Core.bsv
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@@ -1319,7 +1319,7 @@ module mkCore#(CoreId coreId)(Core);
l2Tlb.updateVMInfo(vmI, vmD);
let startpc = csrf.dpc_read;
fetchStage.redirect (cast(startpc));
fetchStage.redirect (PredState{pc: cast(startpc)});
renameStage.debug_resume;
commitStage.debug_resume;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -747,7 +747,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
? 4
: 1));
csrf.dcsr_cause_write (dcsr_cause);
csrf.dpc_write (cast(trap.pc));
csrf.dpc_write (cast(trap.ps.pc));
// Tell fetch stage to wait for redirect
// Note: rule doCommitTrap_flush may have done this already; redundant call is ok.

20
src_SSITH_P3/xilinx_ip/component.xml
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@@ -2696,6 +2696,26 @@
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/module_capChecksExec.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/module_capChecksMem.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/mkAxiLowPower.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/mkPLIC_16_CoreNumX2_7.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/module_decode.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>