Peter Rugg
7c0dad18d6
Deal with separate kinds of sealing more explicitly
2020-05-13 12:02:03 +01:00
jon
d3e0908785
Check PCC bounds in rename.
2020-04-28 19:08:07 +01:00
Peter Rugg
28c09ef1df
Factor out SCR definitions
2020-04-23 13:15:26 +01:00
Peter Rugg
7db3fa539f
Add ALU bounds check
2020-04-20 11:21:51 +01:00
Peter Rugg
f1e04486b7
Work on SCR-related instructions
2020-04-16 20:53:08 +01:00
Peter Rugg
34c4e0f2fa
Comment out user exception delegation SCRs since the corresponding CSRs are not yet supported
2020-04-16 20:43:44 +01:00
jon
850e632140
Changes for CJALR to work in a basic case, as well as piping CHERI exceptions through to commit, though the register isn't piped and I've undone some useful work for that piping. Oh well.
2020-04-06 18:18:05 +01:00
Peter Rugg
4ce8f54903
Add initial exception checks
2020-04-06 12:26:19 +01:00
Jonathan Woodruff
db41e2b9ed
An initial implementation of mccsr.
2020-03-27 17:47:02 +00:00
Jonathan Woodruff
c035f359e8
Merge branch 'CHERI' into pdr32-tmp
...
and get it to build!
2020-03-26 18:03:58 +00:00
Jonathan Woodruff
2aa902f61a
Change tabs to 8 spaces, this time being careful to do this only in BSV files.
2020-03-23 14:44:39 +00:00
Jonathan Woodruff
a6e5a7bff0
Revert "Fix whitespace in src_Core directory."
...
This reverts commit a137a6ede7
2020-03-23 14:40:02 +00:00
Jonathan Woodruff
a137a6ede7
Fix whitespace in src_Core directory.
...
Replace all tabs with 8 spaces.
2020-03-23 14:28:00 +00:00
Jonathan Woodruff
a299a763ed
Add a special capability register file and pass it's interfaces to all the places that the current CSR file goes.
...
We may need to trim some of these later, but most of them seem like places that we'll need access.
2020-03-23 10:10:11 +00:00
Jonathan Woodruff
c97ee15851
A couple initial files with beginnings of CHERI support.
2020-03-20 15:34:18 +00:00
rsnikhil
b00f1d2eec
Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D
...
We were reporting the incremental value of fflags (=0)
instead of the final value of fflags (same as pre-value, which may not be 0).
2020-03-09 14:47:20 -04:00
rsnikhil
976494a8ff
Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.
...
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty". Tandem Verification
trace-generation was not reporting this update.
2020-03-08 21:29:30 -04:00
rsnikhil
6078b7ce19
Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow
2020-01-29 13:19:31 -05:00
rsnikhil
ee24a93944
Initial load of files
2019-03-26 14:49:40 -04:00
