Cheri-research/Toooba
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976494a8ffae34b36556e2e63be6bf3d59afd6b6
Toooba/src_Core/ISA
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rsnikhil 976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. 
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.
2020-03-08 21:29:30 -04:00
..
ISA_Decls_C.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ISA_Decls_Priv_M.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ISA_Decls_Priv_S.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ISA_Decls.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TV_Info.bsv
Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.
2020-03-08 21:29:30 -04:00