3 Commits

Author	SHA1	Message	Date
rsnikhil	976494a8ff	Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. ... When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also changes MSTATUS.FS and, by implication, MSTATUS.SD because the floating point state has become "dirty". Tandem Verification trace-generation was not reporting this update.	2020-03-08 21:29:30 -04:00
rsnikhil	6078b7ce19	Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow	2020-01-29 13:19:31 -05:00
rsnikhil	ee24a93944	Initial load of files	2019-03-26 14:49:40 -04:00