4 Commits

Author	SHA1	Message	Date
rsnikhil	db114186af	More progress towards Tandem Verification trace generation (detail below) ... Now handling all Alu and Fpu pipeline outputs, traps and xRets. Still todo: (1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg) (2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.	2020-02-10 15:08:08 -05:00
rsnikhil	c0ae2776e8	Further additions to Tandem Verification trace info. ... Rd value (destination register) of Integer ops supported Trap updates (priv and CSR updates) supported. Still pending: Memory ops Rd value, Fpu Rd value	2020-02-07 23:10:53 -05:00
rsnikhil	af0b1ef415	Incremental additions to Tandem Verification trace gen	2020-02-06 20:46:26 -05:00
rsnikhil	6078b7ce19	Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow	2020-01-29 13:19:31 -05:00