l1 tlb performance metrics working

enabled performance counters
2026-04-09 13:31:59 +01:00 · 2026-04-09 01:13:56 +01:00
26 changed files with 4311 additions and 286066 deletions
--- a/0001-enabled-performance-counters.patch
+++ b/0001-enabled-performance-counters.patch
--- a/Tests/isa/testC
+++ b/Tests/isa/testC
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -60,12 +60,12 @@ import TlbTypes::*;
 import SynthParam::*;
 import VerificationPacket::*;
 import Performance::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import BlueUtils::*;
 import StatCounters::*;
 import GenerateHPMVector::*;
-`endif
+// `endif
 import HasSpecBits::*;
 import Exec::*;
 import FetchStage::*;
@@ -212,10 +212,10 @@ interface Core;
   interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method Action events_llc(EventsLL events);
    method Action events_tgc(EventsTGC events);
-`endif
+// `endif
 endinterface

 // fixpoint to instantiate modules
@@ -268,9 +268,9 @@ module mkCore#(CoreId coreId)(Core);
   Vector #(SupSize, FIFOF #(Trace_Data2)) v_f_to_TV <- replicateM (mkFIFOF);
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   Array #(Reg #(EventsCore)) hpm_core_events <- mkDRegOR (2, unpack (0));
-`endif
+// `endif

   // ================================================================

@@ -298,7 +298,7 @@ module mkCore#(CoreId coreId)(Core);
    SpecTagManager specTagManager <- mkSpecTagManager;
    ReorderBufferSynth rob <- mkReorderBufferSynth;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    Vector#(SupSize, Bag#(BagSz, CapMem, CapMem)) bags;
    for(Integer i = 0; i < valueof(SupSize); i=i+1) begin
@@ -309,7 +309,7 @@ module mkCore#(CoreId coreId)(Core);
        returnBags[i] <- mkSmallBag;
    end
 `endif
-`endif
+// `endif

    // We have two scoreboards: one conservative and other aggressive
    // - Aggressive sb is checked at rename stage, so inst after rename may be issued early
@@ -437,7 +437,7 @@ module mkCore#(CoreId coreId)(Core);
                method Bool pauseExecute = globalSpecUpdate.pendingIncorrectSpec;
                method correctSpec = globalSpecUpdate.correctSpec[finishAluCorrectSpecPort(i)].put;
                method doStats = doStatsReg._read;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
                method Bool checkTarget(CapMem ppc);
                    Bool ret = False;
@@ -454,7 +454,7 @@ module mkCore#(CoreId coreId)(Core);
                    return ret;
                endmethod
 `endif
-`endif
+// `endif
            endinterface);
            aluExe[i] <- mkAluExePipeline(aluExeInput);
            // truly call fetch method to train branch predictor
@@ -512,12 +512,12 @@ module mkCore#(CoreId coreId)(Core);
            method setRegReadyAggr_forward = writeAggr(forwardWrAggrPort);
            method writeRegFile = writeCons(memWrConsPort);
            method doStats = doStatsReg._read;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
            method rob_getPredPC = rob.getOrigPredPC[valueof(AluExeNum)].get; // last getOrigPredPC port
            method rob_getOrig_Inst = rob.getOrig_Inst[valueof(AluExeNum)].get; // last getOrig_Inst port
 `endif
-`endif
+// `endif
        endinterface);
        let memExe <- mkMemExePipeline(memExeInput);

@@ -580,7 +580,7 @@ module mkCore#(CoreId coreId)(Core);

    // performance counters
    Reg#(Bool) doStats = coreFix.doStatsIfc; // whether data is collected
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // OOO execute stag (in AluExePipeline and MemExePipeline)

    // commit stage (many in CommitStage.bsv)
@@ -608,7 +608,7 @@ module mkCore#(CoreId coreId)(Core);

    // FIFO of perf resp
    FIFO#(ProcPerfResp) perfRespQ <- mkFIFO1;
-`endif
+// `endif
    // FIFO of perf req
    FIFO#(ProcPerfReq) perfReqQ <- mkFIFO1;

@@ -721,7 +721,7 @@ module mkCore#(CoreId coreId)(Core);
 `endif
        endmethod

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
            for(Integer i = 0; i < valueof(SupSize); i=i+1) begin
@@ -739,7 +739,7 @@ module mkCore#(CoreId coreId)(Core);
            end
        endmethod
 `endif
-`endif
+// `endif

 `ifdef INCLUDE_TANDEM_VERIF
       interface v_to_TV = map (toPut, v_f_to_TV);
@@ -842,7 +842,7 @@ module mkCore#(CoreId coreId)(Core);
        fetchStage.flush_predictors;
        // $display ("%0d: %m.rule flushBrPred", cur_cycle);
    endrule
-`endif
+// `endif

 `ifdef SELF_INV_CACHE
    // Use wires to capture flush regs and empty signals. This is ok because
@@ -914,7 +914,7 @@ module mkCore#(CoreId coreId)(Core);
    endrule
 `endif

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // incr cycle count
    (* fire_when_enabled, no_implicit_conditions *)
    rule incCycleCnt(doStats);
@@ -1170,9 +1170,9 @@ module mkCore#(CoreId coreId)(Core);
            perfRespQ.enq(r);
        end
    endrule
-`endif
+// `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
     // ================================================================
     // Performance counters
     // Each cache and TLB pair uses the same struct (EventsCache), but the cache accesses
@@ -1220,7 +1220,7 @@ module mkCore#(CoreId coreId)(Core);
     rule rl_send_perf_evts;
          csrf.send_performance_events (events);
     endrule
-`endif
+// `endif

 `ifdef INCLUDE_GDB_CONTROL
   // ================================================================
@@ -1531,18 +1531,18 @@ module mkCore#(CoreId coreId)(Core);

    interface CoreIndInv coreIndInv;
        method ActionValue#(ProcPerfResp) perfResp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            let r = perfReqQ.first;
-            return ProcPerfResp {
-                loc: r.loc,
-                pType: r.pType,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             let r = perfReqQ.first;
+//             return ProcPerfResp {
+//                 loc: r.loc,
+//                 pType: r.pType,
+//                 data: 0
+//             };
+// `endif
        endmethod

        method terminate = csrf.terminate;
@@ -1602,9 +1602,9 @@ module mkCore#(CoreId coreId)(Core);
   interface v_to_TV = map (toGet, v_f_to_TV);
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method events_llc = events_llc_reg._write;
    method events_tgc = events_tgc_reg._write;
-`endif
+// `endif

 endmodule
--- a/src_Core/CPU/CsrFile.bsv
+++ b/src_Core/CPU/CsrFile.bsv
@@ -58,10 +58,10 @@ import ISA_Decls_CHERI::*;

 import Cur_Cycle  :: *;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor :: *;
 import StatCounters::*;
-`endif
+// `endif

 // ================================================================
 // Project imports from Toooba
@@ -184,10 +184,10 @@ interface CsrFile;
   method Action dcsr_cause_write (Bit #(3)  dcsr_cause);

 `endif
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   (* always_ready, always_enabled *)
   method Action send_performance_events (Vector #(No_Of_Evts, Bit #(Report_Width)) evts);
-`endif
+// `endif
 endinterface

 // Fancy Reg functions
@@ -242,7 +242,7 @@ function Reg#(t) addWriteSideEffect(Reg#(t) r, Action a);
    endinterface);
 endfunction

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 interface PerfCountersVec;
    interface Vector#(No_Of_Ctrs, Reg#(Data)) counter_vec;
    interface Vector#(No_Of_Ctrs, Reg#(Data)) event_vec;
@@ -289,7 +289,7 @@ module mkPerfCountersToooba (PerfCountersVec);
    endinterface;
    method send_performance_events = perf_counters.send_performance_events;
 endmodule
-`endif
+// `endif

 function Bool has_csr_permission(CSR csr, Bit#(2) prv, Bool write);
    Bit#(12) csr_index = pack(csr);
@@ -754,7 +754,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
   Reg #(Data) rg_dscratch1 <- mkConfigRegU;
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   PerfCountersVec perf_counters <- mkPerfCountersToooba;

   //Reg #(Bit #(2)) rg_ctr_inhib_lsb   <- mkReg (0);
@@ -762,7 +762,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
   //Bit #(3) ctr_inhibit_lsb = { rg_ctr_inhib_lsb [1], 0, rg_ctr_inhib_lsb [0] };
   //Word ctr_inhibit = zeroExtend ({ perf_counters.read_ctr_inhibit, ctr_inhibit_lsb });
   //CSR_Addr no_of_ctrs = fromInteger (valueOf (No_Of_Ctrs));
-`endif
+// `endif

 `ifdef SECURITY
    // sanctum machine CSRs
@@ -832,25 +832,25 @@ module mkCsrFile #(Data hartid)(CsrFile);
    Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap);
    Ehr#(2, CapReg) mepcc_reg  <- mkConfigEhr(defaultValue);

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    // Performance monitoring
    Reg#(Bit#(1)) mcountinhibit_cy_reg <- mkCsrReg(0);
    Reg#(Bit#(1)) mcountinhibit_ir_reg <- mkCsrReg(0);
    Reg#(Data) mcountinhibit_reg = concatReg5(readOnlyReg(32'h00000000), perf_counters.inhibit, mcountinhibit_ir_reg, readOnlyReg(1'b0), mcountinhibit_cy_reg);
-`endif
+// `endif

    rule incCycle;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        if(!unpack(mcountinhibit_cy_reg)) mcycle_ehr[1] <= mcycle_ehr[1] + 1;
-`else
-        mcycle_ehr[1] <= mcycle_ehr[1] + 1;
-`endif
+// `else
+//         mcycle_ehr[1] <= mcycle_ehr[1] + 1;
+// `endif
    endrule

    // Function for getting a csr given an index
    function Reg#(Data) get_csr(CSR csr);
        Reg#(Data) ret = readOnlyReg(64'b0);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        let c = csr.addr;
        if ((csrAddrMHPMCOUNTER3.addr <= c) && (c <= csrAddrMHPMCOUNTER31.addr))
            ret = perf_counters.counter_vec[c-csrAddrMHPMCOUNTER3.addr];
@@ -858,7 +858,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
            ret = perf_counters.event_vec[c - csrAddrMHPMEVENT3.addr];
        if ((csrAddrHPMCOUNTER3.addr <= c) && (c <= csrAddrHPMCOUNTER31.addr))
            ret = perf_counters.counter_vec[c-csrAddrHPMCOUNTER3.addr];
-`endif
+// `endif
        return (case (csr)
            // User CSRs
            csrAddrFFLAGS:     fflags_csr;
@@ -901,10 +901,10 @@ module mkCsrFile #(Data hartid)(CsrFile);
            csrAddrMIMPID:     mimpid_csr;
            csrAddrMHARTID:    mhartid_csr;
            csrAddrMCCSR:      mccsr_csr;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
            //csrAddrMCOUNTERINHIBIT: perf_counters.inhibit;
            csrAddrMCOUNTERINHIBIT: mcountinhibit_reg;
-`endif
+// `endif
 `ifdef SECURITY
            csrAddrMEVBASE:    mevbase_csr;
            csrAddrMEVMASK:    mevmask_csr;
@@ -1396,11 +1396,11 @@ module mkCsrFile #(Data hartid)(CsrFile);
    };

    method Action incInstret(SupCnt x);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        if(!unpack(mcountinhibit_ir_reg))  minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x);
-`else
-        minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x);
-`endif
+// `else
+        // minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x);
+// `endif
    endmethod

    method Action setTime(Data t);
@@ -1473,7 +1473,7 @@ module mkCsrFile #(Data hartid)(CsrFile);

 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method send_performance_events = perf_counters.send_performance_events;
-`endif
+// `endif
 endmodule
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -79,9 +79,9 @@ import MMIOAddrs::*;
 import MMIOCore::*;
 import DramCommon::*;
 import Performance::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 // ----------------
 // From Tooba
@@ -180,7 +180,7 @@ module mkProc (Proc_IFC);
       statReqs.deq;
   endrule

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   Reg#(EventsTGC) events_tgc_reg <- mkRegU;
   rule broadcastPerfEvents;
       for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
@@ -188,7 +188,7 @@ module mkProc (Proc_IFC);
           core[j].events_tgc(events_tgc_reg);
       end
   endrule
-`endif
+// `endif

   // ================================================================
   // Stub out deadlock and renameDebug interfaces
@@ -361,9 +361,9 @@ module mkProc (Proc_IFC);
   interface v_to_TV = core [0].v_to_TV;
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method events_tgc = events_tgc_reg._write;
-`endif
+// `endif

 endmodule: mkProc

--- a/src_Core/CPU/Proc_IFC.bsv
+++ b/src_Core/CPU/Proc_IFC.bsv
@@ -43,9 +43,9 @@ import Fabric_Defs :: *;
 import SoC_Map :: *;
 import CCTypes :: *;
 import ProcTypes :: *;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 `ifdef INCLUDE_GDB_CONTROL
 import DM_CPU_Req_Rsp :: *;
@@ -140,9 +140,9 @@ interface Proc_IFC;
   interface Vector #(SupSize, Get #(Trace_Data2)) v_to_TV;
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method Action events_tgc(EventsTGC events);
-`endif
+// `endif

 endinterface

--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -78,9 +78,9 @@ import CacheCore  :: *;
 // ----------------
 // From RISCY-ooo
 import ProcTypes    :: *;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 // ----------------
 // From Toooba
@@ -241,7 +241,7 @@ module mkCoreW_reset #(Reset porReset)
   mkConnection (tagController.master, tag_controller_deburster.slave, reset_by all_harts_reset);
   */

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   rule report_tagController_events;
      EventsCacheCore cache_core_evts = tagController.events;
      EventsTGC evts = unpack(0);
@@ -256,7 +256,7 @@ module mkCoreW_reset #(Reset porReset)
 `endif
      proc.events_tgc(evts);
   endrule
-`endif
+// `endif

   // PLIC (Platform-Level Interrupt Controller)
   PLIC_IFC_16_CoreNumX2_7  plic <- mkPLIC_16_CoreNumX2_7 (reset_by all_harts_reset);
--- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
@@ -60,11 +60,11 @@ import Performance::*;
 import LatencyTimer::*;
 import RandomReplace::*;
 import Prefetcher::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import BlueUtils::*;
 import StatCounters::*;
-`endif
+// `endif

 export ICRqStuck(..);
 export IPRqStuck(..);
@@ -105,9 +105,9 @@ interface IBank#(
    // performance
    method Action setPerfStatus(Bool stats);
    method Data getPerfData(L1IPerfType t);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events;
-`endif
+// `endif
 endinterface

 module mkIBank#(
@@ -199,27 +199,27 @@ module mkIBank#(
    LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer;
    Count#(Bit#(32)) addedCRqs <- mkCount(0);
    Count#(Bit#(32)) removedCRqs <- mkCount(0);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(True);
    Count#(Data) ldCnt <- mkCount(0);
    Count#(Data) ldMissCnt <- mkCount(0);
    Count#(Data) ldMissLat <- mkCount(0);
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsL1I)) perf_events <- mkDRegOR (2, unpack (0));
-`endif
+// `endif
    function Action incrReqCnt;
    action
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            ldCnt.incr(1);
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsL1I events = unpack (0);
        events.evt_LD = 1;
        perf_events[0] <= events;
-`endif
+// `endif
        noAction;
    endaction
    endfunction
@@ -227,18 +227,18 @@ module mkIBank#(
    function Action incrMissCnt(cRqIdxT idx);
    action
        let lat <- latTimer.done(idx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            ldMissLat.incr(zeroExtend(lat));
            ldMissCnt.incr(1);
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsL1I events = unpack (0);
        events.evt_LD_MISS_LAT = saturating_truncate(lat);
        events.evt_LD_MISS = 1;
        perf_events[1] <= events;
-`endif
+// `endif
        noAction;
    endaction
    endfunction
@@ -906,26 +906,26 @@ module mkIBank#(
 `endif

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod

    method Data getPerfData(L1IPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            L1ILdCnt: ldCnt;
            L1ILdMissCnt: ldMissCnt;
            L1ILdMissLat: ldMissLat;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events = perf_events[0];
-`endif
+// `endif
 endmodule


--- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
@@ -63,11 +63,11 @@ import Performance::*;
 import LatencyTimer::*;
 import RandomReplace::*;
 import Prefetcher::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import StatCounters::*;
 import BlueUtils::*;
-`endif
+// `endif

 export L1CRqStuck(..);
 export L1PRqStuck(..);
@@ -111,9 +111,9 @@ interface L1Bank#(
    // performance
    method Action setPerfStatus(Bool stats);
    method Data getPerfData(L1DPerfType t);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events;
-`endif
+// `endif
 endinterface

 typedef struct {
@@ -207,7 +207,7 @@ module mkL1Bank#(

    // performance
    LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer; // max 1K cycle latency
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) ldCnt <- mkCount(0);
    Count#(Data) stCnt <- mkCount(0);
@@ -218,13 +218,13 @@ module mkL1Bank#(
    Count#(Data) ldMissLat <- mkCount(0);
    Count#(Data) stMissLat <- mkCount(0);
    Count#(Data) amoMissLat <- mkCount(0);
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsL1D)) perf_events <- mkDRegOR (2, unpack (0));
-`endif
+// `endif
 function Action incrReqCnt(MemOp op);
 action
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    if(doStats) begin
        case(op)
            Ld: ldCnt.incr(1);
@@ -232,8 +232,8 @@ action
            Lr, Sc, Amo: amoCnt.incr(1);
        endcase
    end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    EventsL1D events = unpack (0);
    case(op)
        Ld: events.evt_LD = 1;
@@ -241,7 +241,7 @@ action
        Lr, Sc, Amo: events.evt_AMO = 1;
    endcase
    perf_events[0] <= events;
-`endif
+// `endif
    noAction;
 endaction
 endfunction
@@ -249,7 +249,7 @@ endfunction
 function Action incrMissCnt(MemOp op, cRqIdxT idx);
 action
    let lat <- latTimer.done(idx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    if(doStats) begin
        case(op)
            Ld: begin
@@ -266,8 +266,8 @@ action
            end
        endcase
    end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    EventsL1D events = unpack (0);
    case(op)
        Ld: begin
@@ -284,7 +284,7 @@ action
        end
    endcase
    perf_events[1] <= events;
-`endif
+// `endif
    noAction;
 endaction
 endfunction
@@ -1233,16 +1233,16 @@ endfunction
 `endif

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod

    method Data getPerfData(L1DPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            L1DLdCnt: ldCnt;
            L1DStCnt: stCnt;
            L1DAmoCnt: amoCnt;
@@ -1252,13 +1252,13 @@ endfunction
            L1DLdMissLat: ldMissLat;
            L1DStMissLat: stMissLat;
            L1DAmoMissLat: amoMissLat;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events = perf_events[0];
-`endif
+// `endif
 endmodule


@@ -1495,7 +1495,7 @@ module mkL1Cache#(
        end
        return fold(\+ , d);
    endmethod
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events;
        EventsL1D ret = unpack(0);
        for(Integer i = 0; i < valueof(bankNum); i = i+1) begin
@@ -1503,5 +1503,5 @@ module mkL1Cache#(
        end
        return ret;
    endmethod
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv
@@ -55,11 +55,11 @@ import ConfigReg::*;
 import RandomReplace::*;
 import Prefetcher::*;
 import ProcTypes::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import StatCounters::*;
 import BlueUtils::*;
-`endif
+// `endif

 export LLCRqStuck(..);
 export LLBank(..);
@@ -111,9 +111,9 @@ interface LLBank#(
    // performance
    method Action setPerfStatus(Bool stats);
    method Data getPerfData(LLCPerfType t);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsLL events;
-`endif
+// `endif
 endinterface

 typedef struct {
@@ -241,7 +241,7 @@ module mkLLBank#(
    PrefetcherVector#(TDiv#(childNum, 2)) dataPrefetchers <- mkPrefetcherVector(mkLLDPrefetcher);
    PrefetcherVector#(TDiv#(childNum, 2)) instrPrefetchers <- mkPrefetcherVector(mkLLIPrefetcher);

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(True);
    Count#(Data) dmaMemLdCnt <- mkCount(0);
    Count#(Data) dmaMemLdLat <- mkCount(0);
@@ -257,14 +257,14 @@ module mkLLBank#(
    Count#(Data) upRespDataCnt <- mkCount(0);
    Count#(Data) dmaLdReqCnt <- mkCount(0);
    Count#(Data) dmaStReqCnt <- mkCount(0);
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsLL)) perf_events <- mkDRegOR (2, unpack (0));
-`endif
+// `endif
 function Action incrMissCnt(cRqIndexT idx, Bool isDma, Bool isInstructionAccess);
 action
    let lat <- latTimer.done(idx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    if(doStats) begin
        if(isDma) begin
            dmaMemLdCnt.incr(1);
@@ -279,13 +279,13 @@ action
            normalMemLdLat.incr(zeroExtend(lat));
        end
    end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    EventsLL events = unpack (0);
    events.evt_LD_MISS_LAT = saturating_truncate(lat); // Don't support seperate DMA counts.
    events.evt_LD_MISS = 1;
    perf_events[1] <= events;
-`endif
+// `endif
 endaction
 endfunction

@@ -485,7 +485,7 @@ endfunction
        );
    endrule

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // perf stats: insert new cRq fails because of full MSHR
    rule cRqTransfer_new_child_block(
        !cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Child) && doStats
@@ -504,7 +504,7 @@ endfunction
            mshrBlocks.incr(1);
        end
    endrule
-`endif
+// `endif

    // insert new cRq from DMA to MSHR and send to pipeline
    rule cRqTransfer_new_dma(!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma));
@@ -536,7 +536,7 @@ endfunction
            fshow(r), " ; ",
            fshow(cRq)
        );
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            if(write) begin
                dmaStReqCnt.incr(1);
@@ -545,10 +545,10 @@ endfunction
                dmaLdReqCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // perf stats: insert new cRq fails because of full MSHR
    rule cRqTransfer_new_dma_block(
        !cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma) && doStats
@@ -568,7 +568,7 @@ endfunction
            mshrBlocks.incr(1);
        end
    endrule
-`endif
+// `endif

    // send downgrade resp from child to pipeline
    rule cRsTransfer;
@@ -577,14 +577,14 @@ endfunction
        pipeline.send(CRs (cRs));
       if (verbose)
        $display("%t LL %m cRsTransfer: ", $time, fshow(cRs));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            downRespCnt.incr(1);
            if(isValid(cRs.data)) begin
                downRespDataCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    rule discardPrefetchRqResult(rsToCIndexQ.notEmpty && cRqIsPrefetch[rsToCIndexQ.first.cRqId]);
@@ -596,14 +596,14 @@ endfunction

    // mem resp for child req, will refill cache, send it to pipeline
    (* descending_urgency = "mRsTransfer, cRsTransfer, discardPrefetchRqResult, cRqTransfer_retry, cRqTransfer_new_child, cRqTransfer_new_dma, createInstrPrefetchRq, createDataPrefetchRq" *)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // stop mshr block stats when other higher priority req is being sent to
    // pipeline
    (* preempts = "mRsTransfer, cRqTransfer_new_child_block" *)
    (* preempts = "mRsTransfer, cRqTransfer_new_dma_block" *)
    (* preempts = "cRsTransfer, cRqTransfer_new_child_block" *)
    (* preempts = "cRsTransfer, cRqTransfer_new_dma_block" *)
-`endif
+// `endif
    rule mRsTransfer(rsFromMQ.first.id.refill);
        // get mem resp cRq index & data
        rsFromMQ.deq;
@@ -742,11 +742,11 @@ endfunction
                toMQ.enq(msg);
                // don't deq info, do ld next time
                doLdAfterReplace <= True;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
                EventsLL events = unpack (0);
                events.evt_ST_MISS = 1;
                perf_events[0] <= events;
-`endif
+// `endif
               if (verbose)
                $display("%t LL %m sendToM: rep then ld: rep: ", $time, fshow(msg));
            end
@@ -832,14 +832,14 @@ endfunction
        }));
        // release MSHR entry
        cRqMshr.sendRsToDmaC.releaseEntry(n);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            upRespCnt.incr(1);
            if(isValid(rsData)) begin
                upRespDataCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    // send downgrade req to child
@@ -930,11 +930,11 @@ endfunction
        );
        // change round-robin
        whichCRq <= whichCRq == fromInteger(valueOf(cRqNum) - 1) ? 0 : whichCRq + 1;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            downReqCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    // Final stage of pipeline: process all kinds of msg
@@ -1657,16 +1657,16 @@ endfunction
    endinterface

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod

    method Data getPerfData(LLCPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            LLCDmaMemLdCnt: dmaMemLdCnt;
            LLCDmaMemLdLat: dmaMemLdLat;
            LLCNormalMemLdCnt: normalMemLdCnt;
@@ -1681,13 +1681,13 @@ endfunction
            LLCUpRespDataCnt: upRespDataCnt;
            LLCDmaLdReqCnt: dmaLdReqCnt;
            LLCDmaStReqCnt: dmaStReqCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
-    `ifdef PERFORMANCE_MONITORING
+    // `ifdef PERFORMANCE_MONITORING
        method EventsLL events = perf_events[0];
-    `endif
+    // `endif
 endmodule

 // Scheduling notes
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
@@ -160,7 +160,7 @@ module mkSelfInvIBank#(
    Fifo#(1, DebugICacheResp) cRqDoneQ <- mkBypassFifo;
 `endif

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) ldCnt <- mkCount(0);
    Count#(Data) ldMissCnt <- mkCount(0);
@@ -186,7 +186,7 @@ module mkSelfInvIBank#(
        end
    endaction
    endfunction
-`endif
+// `endif

    function tagT getTag(Addr a) = truncateLSB(a);

@@ -210,10 +210,10 @@ module mkSelfInvIBank#(
        }));
        // enq to indexQ for in order resp
        cRqIndexQ.enq(n);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: cRq type
        incrReqCnt;
-`endif
+// `endif
       if (verbose)
        $display("%t I %m cRqTransfer: ", $time,
            fshow(n), " ; ",
@@ -267,10 +267,10 @@ module mkSelfInvIBank#(
            fshow(slot), " ; ",
            fshow(cRqToP)
        );
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: start miss timer
        latTimer.start(n);
-`endif
+// `endif
    endrule

    // last stage of pipeline: process req
@@ -475,10 +475,10 @@ module mkSelfInvIBank#(
                "pRs must be a hit"
            );
            cRqHit(cOwner, procRq);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // performance counter: miss cRq
            incrMissCnt(cOwner);
-`endif
+// `endif
        end
        else begin
            doAssert(False, ("pRs owner must match some cRq"));
@@ -498,11 +498,11 @@ module mkSelfInvIBank#(
        waitReconcileDone <= True;
       if (verbose)
        $display("%t I %m startReconcile", $time);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            reconcileCnt.incr(1);
        end
-`endif
+// `endif
    endrule
    rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
        needReconcile <= False;
@@ -573,21 +573,21 @@ module mkSelfInvIBank#(
    endmethod

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod

    method Data getPerfData(L1IPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            L1ILdCnt: ldCnt;
            L1ILdMissCnt: ldMissCnt;
            L1ILdMissLat: ldMissLat;
            L1IReconcileCnt: reconcileCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
@@ -211,7 +211,7 @@ module mkSelfInvL1Bank#(
    Reg#(Bool) waitReconcileDone <- mkReg(False);

    // performance
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) ldCnt <- mkCount(0);
    Count#(Data) stCnt <- mkCount(0);
@@ -260,7 +260,7 @@ module mkSelfInvL1Bank#(
        end
    endaction
    endfunction
-`endif
+// `endif

    function tagT getTag(Addr a) = truncateLSB(a);

@@ -296,10 +296,10 @@ module mkSelfInvL1Bank#(
            addr: r.addr, 
            mshrIdx: n
        }));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: cRq type
        incrReqCnt(r.op);
-`endif
+// `endif
       if (verbose)
        $display("%t L1 %m cRqTransfer_new: ", $time, 
            fshow(n), " ; ",
@@ -422,10 +422,10 @@ module mkSelfInvL1Bank#(
            fshow(cRqToP)
        );
        doAssert(slot.cs == I, "we always self-inv before req to parent");
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: start miss timer
        latTimer.start(n);
-`endif
+// `endif
    endrule

    // last stage of pipeline: process req
@@ -550,11 +550,11 @@ module mkSelfInvL1Bank#(
            );
            // release MSHR entry
            cRqMshr.pipelineResp.releaseEntry(n);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(doStats && needSelfInv) begin
                selfInvCnt.incr(1);
            end
-`endif
+// `endif
        end
        else begin
            processAmo <= Valid (AmoHitInfo {
@@ -871,10 +871,10 @@ module mkSelfInvL1Bank#(
                ("pRs must be a hit")
            );
            cRqHit(cOwner, procRq, True);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // performance counter: miss cRq
            incrMissCnt(procRq.op, cOwner);
-`endif
+// `endif
        end
        else begin
            doAssert(False, ("pRs owner must match some cRq"));
@@ -966,11 +966,11 @@ module mkSelfInvL1Bank#(
        waitReconcileDone <= True;
       if (verbose)
        $display("%t L1 %m startReconcile", $time);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            reconcileCnt.incr(1);
        end
-`endif
+// `endif
    endrule
    rule completeReconcile(needReconcile && waitReconcileDone && pipeline.reconcile_done);
        needReconcile <= False;
@@ -1021,16 +1021,16 @@ module mkSelfInvL1Bank#(
    endmethod

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod 

    method Data getPerfData(L1DPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            L1DLdCnt: ldCnt;
            L1DStCnt: stCnt;
            L1DAmoCnt: amoCnt;
@@ -1042,7 +1042,7 @@ module mkSelfInvL1Bank#(
            L1DAmoMissLat: amoMissLat;
            L1DSelfInvCnt: selfInvCnt;
            L1DReconcileCnt: reconcileCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
--- a/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
@@ -213,7 +213,7 @@ module mkSelfInvLLBank#(
 `endif

    // performance
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) dmaMemLdCnt <- mkCount(0);
    Count#(Data) dmaMemLdLat <- mkCount(0);
@@ -245,7 +245,7 @@ module mkSelfInvLLBank#(
        end
    endaction
    endfunction
-`endif
+// `endif

    function tagT getTag(Addr a) = truncateLSB(a);

@@ -373,7 +373,7 @@ module mkSelfInvLLBank#(
        );
    endrule

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // perf stats: insert new cRq fails because of full MSHR
    rule cRqTransfer_new_child_block(
        !cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Child) && doStats
@@ -392,7 +392,7 @@ module mkSelfInvLLBank#(
            mshrBlocks.incr(1);
        end
    endrule
-`endif
+// `endif

    // insert new cRq from DMA to MSHR and send to pipeline
    rule cRqTransfer_new_dma(!cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma));
@@ -422,7 +422,7 @@ module mkSelfInvLLBank#(
            fshow(r), " ; ",
            fshow(cRq)
        );
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            if(write) begin
                dmaStReqCnt.incr(1);
@@ -431,10 +431,10 @@ module mkSelfInvLLBank#(
                dmaLdReqCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // perf stats: insert new cRq fails because of full MSHR
    rule cRqTransfer_new_dma_block(
        !cRqRetryIndexQ.notEmpty && newCRqSrc == Valid (Dma) && doStats
@@ -454,7 +454,7 @@ module mkSelfInvLLBank#(
            mshrBlocks.incr(1);
        end
    endrule
-`endif
+// `endif

    // send downgrade resp from child to pipeline
    rule cRsTransfer;
@@ -462,26 +462,26 @@ module mkSelfInvLLBank#(
        cRsFromCT cRs = rsFromCQ.first;
        pipeline.send(CRs (cRs));
        $display("%t LL %m cRsTransfer: ", $time, fshow(cRs));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            downRespCnt.incr(1);
            if(isValid(cRs.data)) begin
                downRespDataCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    // mem resp for child req, will refill cache, send it to pipeline
    (* descending_urgency = "mRsTransfer, cRsTransfer, cRqTransfer_retry, cRqTransfer_new_child, cRqTransfer_new_dma" *)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // stop mshr block stats when other higher priority req is being sent to
    // pipeline
    (* preempts = "mRsTransfer, cRqTransfer_new_child_block" *)
    (* preempts = "mRsTransfer, cRqTransfer_new_dma_block" *)
    (* preempts = "cRsTransfer, cRqTransfer_new_child_block" *)
    (* preempts = "cRsTransfer, cRqTransfer_new_dma_block" *)
-`endif
+// `endif
    rule mRsTransfer(rsFromMQ.first.id.refill);
        // get mem resp cRq index & data
        rsFromMQ.deq;
@@ -504,10 +504,10 @@ module mkSelfInvLLBank#(
            fshow(cRq), " ; ",
            fshow(cSlot), " ; "
        );
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: normal miss lat and cnt
        incrMissCnt(n, False);
-`endif
+// `endif
    endrule

    // this mem resp is just for a DMA req, won't go into pipeline to refill cache
@@ -518,10 +518,10 @@ module mkSelfInvLLBank#(
        // save data into cRq mshr & send to DMA resp IndexQ
        cRqMshr.mRsDeq.setData(mRs.id.mshrIdx, Valid (mRs.data));
        rsLdToDmaIndexQ_mRsDeq.enq(mRs.id.mshrIdx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter: dma miss lat and cnt
        incrMissCnt(mRs.id.mshrIdx, True);
-`endif
+// `endif
    endrule

    // send rd/wr to mem
@@ -558,10 +558,10 @@ module mkSelfInvLLBank#(
            $display("%t LL %m sendToM: load only: ", $time, fshow(msg));
            doAssert(!isValid(data), "cannot have data");
            doAssert(!doLdAfterReplace, "doLdAfterReplace should be false");
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // performance counter: start miss timer
            latTimer.start(n);
-`endif
+// `endif
 `ifdef DEBUG_DMA
            if(cRq.id matches tagged Dma .dmaId) begin
                dmaRdMissQ.enq(dmaId); // DMA read takes effect
@@ -603,10 +603,10 @@ module mkSelfInvLLBank#(
                toMInfoQ.deq;
                doLdAfterReplace <= False;
                $display("%t LL %m sendToM: rep then ld: ld: ", $time, fshow(msg));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                // performance counter: start miss timer
                latTimer.start(n);
-`endif
+// `endif
            end
            else begin // do write back part
                toMemT msg = Wb (WbMemRs {
@@ -698,14 +698,14 @@ module mkSelfInvLLBank#(
        }));
        // release MSHR entry
        cRqMshr.sendRsToDmaC.releaseEntry(n);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            upRespCnt.incr(1);
            if(isValid(rsData)) begin
                upRespDataCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    // send downgrade req to child
@@ -787,11 +787,11 @@ module mkSelfInvLLBank#(
        );
        // change round-robin
        whichCRq <= whichCRq == fromInteger(valueOf(cRqNum) - 1) ? 0 : whichCRq + 1;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            downReqCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    // Final stage of pipeline: process all kinds of msg
@@ -1417,16 +1417,16 @@ module mkSelfInvLLBank#(
    endinterface

    method Action setPerfStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        doStats <= stats;
-`else
-        noAction;
-`endif
+// `else
+//         noAction;
+// `endif
    endmethod

    method Data getPerfData(LLCPerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            LLCDmaMemLdCnt: dmaMemLdCnt;
            LLCDmaMemLdLat: dmaMemLdLat;
            LLCNormalMemLdCnt: normalMemLdCnt;
@@ -1439,7 +1439,7 @@ module mkSelfInvLLBank#(
            LLCUpRespDataCnt: upRespDataCnt;
            LLCDmaLdReqCnt: dmaLdReqCnt;
            LLCDmaStReqCnt: dmaStReqCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -64,11 +64,11 @@ import Bypass::*;
 import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import BlueUtils::*;
 import StatCounters::*;
 import DReg::*;
-`endif
+// `endif


 import Cur_Cycle :: *;
@@ -220,14 +220,14 @@ interface AluExeInput;
    // performance
    method Bool doStats;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    // check previous branch targets
    method Bool checkTarget(CapMem ppc);
    // check (previous) return targets
    method Bool checkReturnTarget(CapMem ppc);
 `endif
-`endif
+// `endif
 endinterface

 interface AluExePipeline;
@@ -237,11 +237,11 @@ interface AluExePipeline;
    interface SpeculationUpdate specUpdate;
    method Data getPerf(ExeStagePerfType t);

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    method EventsTransExe events;
 `endif
-`endif
+// `endif
 endinterface

 module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
@@ -260,18 +260,18 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
    Integer exeSendBypassPort = 0;
    Integer finishSendBypassPort = 1;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    Array#(Reg#(EventsTransExe)) events_reg <- mkDRegOR(2, unpack(0));
 `endif
-`endif
+// `endif

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // performance counters
    Count#(Data) exeRedirectBrCnt <- mkCount(0);
    Count#(Data) exeRedirectJrCnt <- mkCount(0);
    Count#(Data) exeRedirectOtherCnt <- mkCount(0);
-`endif
+// `endif

    rule doDispatchAlu;
        rsAlu.doDispatch;
@@ -336,7 +336,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
        let ppc = inIfc.rob_getPredPC(x.tag);
        let orig_inst = inIfc.rob_getOrig_Inst (x.tag);

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        let ppc_addr = getAddr(ppc);
        let pc_addr = getAddr(pc);
@@ -361,7 +361,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
            end
        end
 `endif
-`endif
+// `endif

 `ifdef KONATA 
        $display("KONATAE\t%0d\t%0d\t0\tAlu1", cur_cycle, x.u_id);
@@ -511,7 +511,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
        $display("KONATAS\t%0d\t%0d\t0\tAlu4\t%0d", cur_cycle, x.u_id, cur_cycle);
        $fflush;
 `endif
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        // get PC and PPC
        let pc = getAddr(x.controlFlow.pc);
@@ -523,7 +523,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
            events_reg[0] <= events;
        end
 `endif
-`endif
+// `endif

        let train_spec_bits = 0;
 `ifdef NO_SPEC_TRAINING
@@ -554,7 +554,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
            if (verbose)
                $display("alu mispredict pc: %x, nextPc: %x, %d",
                         x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // performance counter
            if(inIfc.doStats) begin
                case(x.iType)
@@ -563,7 +563,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
                    default: exeRedirectOtherCnt.incr(1);
                endcase
            end
-`endif
+// `endif
        end
        else (* nosplit *) begin
            // release spec tag
@@ -603,19 +603,19 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);

    method Data getPerf(ExeStagePerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            ExeRedirectBr: exeRedirectBrCnt;
            ExeRedirectJr: exeRedirectJrCnt;
            ExeRedirectOther: exeRedirectOtherCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    method events = events_reg[0];
 `endif
-`endif
+// `endif

 endmodule
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -66,9 +66,9 @@ import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
 import RegFile::*; // Just for the interface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 `ifdef RVFI
 import RVFI_DII_Types::*;
@@ -151,14 +151,14 @@ interface CommitInput;
    // deadlock check
    method Bool checkDeadlock;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    // update branch targets
    method Action updateTargets(Vector#(SupSize, Maybe#(CapMem)) targets);
    // update return targets
    method Action updateReturnTargets(Vector#(SupSize, Maybe#(CapMem)) returnTargets);
 `endif
-`endif
+// `endif

 `ifdef INCLUDE_TANDEM_VERIF
    interface Vector #(SupSize, Put #(Trace_Data2)) v_to_TV;
@@ -197,9 +197,9 @@ interface CommitStage;
   method Bool is_debug_halted;
   method Action debug_resume;
 `endif
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   method EventsCore events;
-`endif
+// `endif
 endinterface

 // we apply actions the end of commit rule
@@ -422,7 +422,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
    end

    // commit stage performance counters
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // inst
    Count#(Data) instCnt <- mkCount(0);
    Count#(Data) userInstCnt <- mkCount(0);
@@ -451,11 +451,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
    Count#(Data) flushSecurityCnt <- mkCount(0);
    Count#(Data) flushBPCnt <- mkCount(0);
    Count#(Data) flushCacheCnt <- mkCount(0);
-`endif
+// `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    Reg#(EventsCore) events_reg <- mkDReg(unpack(0));
-`endif
+// `endif

 `ifdef RVFI
    // RVFI trace report. Not an input?
@@ -568,11 +568,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        if(flushTlb) begin
 `endif
            inIfc.setFlushTlbs;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                flushTlbCnt.incr(1);
            end
-`endif
+// `endif
        end
        // notify TLB to keep update of CSR changes
        inIfc.setUpdateVMInfo;
@@ -596,28 +596,28 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        // valid because these wrong path inst/req will not interfere with
        // whatever CSR changes we are making now.
        if(flushSecurity) begin
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                flushSecurityCnt.incr(1);
            end
-`endif
+// `endif

 `ifndef DISABLE_SECURE_FLUSH_BP
            inIfc.setFlushBrPred;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                flushBPCnt.incr(1);
            end
-`endif
+// `endif
 `endif

 `ifndef DISABLE_SECURE_FLUSH_CACHE
            inIfc.setFlushCaches;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                flushCacheCnt.incr(1);
            end
-`endif
+// `endif
 `endif
        end

@@ -734,7 +734,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        // faulting mem inst may have claimed phy reg, we should not commit it;
        // instead, we kill the renaming by calling killAll

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter
        if(inIfc.doStats) begin
            if(trap matches tagged Exception .e) begin
@@ -744,15 +744,15 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                interruptCnt.incr(1);
            end
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsCore events = unpack(0);
        events.evt_TRAP = 1;
        if(trap matches tagged Interrupt .i) begin
            events.evt_INTERRUPT = 1;
        end
        events_reg <= events;
-`endif
+// `endif
        // checks
        doAssert(x.rob_inst_state == Executed, "must be executed");
        doAssert(x.spec_bits == 0, "cannot have spec bits");
@@ -873,7 +873,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        // the killed Ld should have claimed phy reg, we should not commit it;
        // instead, we have kill the renaming by calling killAll

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            case(killBy)
                Ld: comLdKillByLdCnt.incr(1);
@@ -881,7 +881,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                Cache: comLdKillByCacheCnt.incr(1);
            endcase
        end
-`endif
+// `endif

        // checks
        doAssert(!x.epochIncremented, "cannot increment epoch before");
@@ -1027,7 +1027,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        $fflush;
        printCommits[0][1] <= tagged Valid x.u_id;
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            comSysCnt.incr(1);
            // inst count stats
@@ -1036,14 +1036,14 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                userInstCnt.incr(1);
            end
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsCore events = unpack(0);
        case(x.iType)
            Fence, FenceI, SFence: events.evt_FENCE = 1;
        endcase
        events_reg <= events;
-`endif
+// `endif
 `ifdef CHECK_DEADLOCK
        commitInst.send;
        if(csrf.decodeInfo.prv == 0) begin
@@ -1148,22 +1148,22 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
       Data     po_mstatus = ?;
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        // update targets vector
        Vector#(SupSize, Maybe#(CapMem)) targets;
        // update return targets vector
        Vector#(SupSize, Maybe#(CapMem)) returnTargets;
 `endif
-`endif
+// `endif
        // compute what actions to take
        for(Integer i = 0; i < valueof(SupSize); i = i+1) begin
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
            Maybe#(CapMem) tar = tagged Invalid;
            Maybe#(CapMem) retTar = tagged Invalid;
 `endif
-`endif
+// `endif
            if(!stop && rob.deqPort[i].canDeq) begin
                let x = rob.deqPort[i].deq_data;
                let inst_tag = rob.deqPort[i].getDeqInstTag;
@@ -1207,7 +1207,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                    // inst can be committed, deq it
                    rob.deqPort[i].deq;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
                    // return address stack link reg is x1 or x5
                    function Bool linkedR(Maybe#(ArchRIndx) register);
@@ -1230,7 +1230,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                        end
                    end
 `endif
-`endif
+// `endif

                    // every inst here should have been renamed, commit renaming
                    regRenamingTable.commit[i].commit;
@@ -1328,12 +1328,12 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
 `endif
                end
            end
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
            targets[i] = tar;
            returnTargets[i] = retTar;
 `endif
-`endif
+// `endif
        end
        rg_serial_num <= rg_serial_num + instret;

@@ -1359,7 +1359,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        end
 `endif

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // performance counter
        if(inIfc.doStats) begin
            // branch stats
@@ -1379,8 +1379,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                supComUserCnt.incr(1);
            end
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsCore events = unpack(0);
        events.evt_BRANCH = zeroExtend(brCnt);
        events.evt_JAL = zeroExtend(jmpCnt);
@@ -1400,7 +1400,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
        inIfc.updateTargets(targets);
        inIfc.updateReturnTargets(returnTargets);
 `endif
-`endif
+// `endif

 `ifdef RVFI
        rvfiQ.enq(rvfis);
@@ -1446,7 +1446,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);

    method Data getPerf(ComStagePerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            InstCnt: instCnt;
            UserInstCnt: userInstCnt;
            SupComUserCnt: supComUserCnt;
@@ -1468,7 +1468,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
            FlushSecurityCnt: flushSecurityCnt;
            FlushBPCnt: flushBPCnt;
            FlushCacheCnt: flushCacheCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
@@ -1509,8 +1509,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
   endmethod
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
   method events = events_reg;
-`endif
+// `endif

 endmodule
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -165,9 +165,9 @@ interface FetchStage;

    // performance
    interface Perf#(DecStagePerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method Bool redirect_evt;
-`endif
+// `endif
 endinterface

 // PC "compression" types to facilitate storing common upper PC bits in a
@@ -471,7 +471,7 @@ module mkFetchStage(FetchStage);

    // performance counters
    Fifo#(1, DecStagePerfType) perfReqQ <- mkCFFifo; // perf req FIFO
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Reg#(Bool) doStats <- mkConfigReg(False);
    // decode stage redirect
    Count#(Data) decRedirectBrCnt <- mkCount(0);
@@ -495,10 +495,10 @@ module mkFetchStage(FetchStage);
            data: d
        });
    endrule
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Reg#(Bool) redirect_evt_reg <- mkDReg(False);
-`endif
+// `endif
 `ifdef KONATA 
    Reg#(Bit#(64)) uid <- mkReg(0);
    Reg#(Bool) k_reset <- mkReg(True);
@@ -856,11 +856,11 @@ module mkFetchStage(FetchStage);
 `endif
      Maybe#(TrainNAP) trainNAP = Invalid; // training data sent to next addr pred
      Bool decode_epoch_local = decode_epoch[0]; // next value for decode epoch
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
      // performance counter: inst being redirect by decode stage
      // Note that only 1 redirection may happen in a cycle
      Maybe#(IType) redirectInst = Invalid;
-`endif
+// `endif
      Bool likely_epoch_change = False;
      Maybe#(CapMem) m_push_addr = Invalid;
      for (Integer i = 0; i < valueof(SupSize); i=i+1) begin
@@ -977,11 +977,11 @@ module mkFetchStage(FetchStage);
                     // train next addr pred when mispredict
                     let last_x16_pc = addPc(pc, ((in.inst_kind == Inst_32b) ? 2 : 0));
                     trainNAP = Valid (TrainNAP {pc: last_x16_pc, nextPc: decode_pred_next_pc});
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                     // performance stats: record decode redirect
                     doAssert(redirectInst == Invalid, "at most 1 decode redirect per cycle");
                     redirectInst = Valid (dInst.iType);
-`endif
+// `endif
                  end
               end // if (!isValid(cause))
               if (isValid(m_push_addr)) trainInfo.ras = trainInfo.ras + 1;
@@ -1049,7 +1049,7 @@ module mkFetchStage(FetchStage);
      if (trainNAP matches tagged Valid .x) begin
         napTrainByDecQ.enq(x);
      end
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
      // performance counter: check whether redirect happens
      if(redirectInst matches tagged Valid .iType &&& doStats) begin
         case(iType)
@@ -1059,7 +1059,7 @@ module mkFetchStage(FetchStage);
            default: decRedirectOtherCnt.incr(1);
         endcase
      end
-`endif
+// `endif
   endrule

   rule reportDecodePc;
@@ -1143,9 +1143,9 @@ module mkFetchStage(FetchStage);
        // this redirect may be caused by a trap/system inst in commit stage
        // we conservatively set wait for flush TODO make this an input parameter
        waitForFlush[2] <= True;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        redirect_evt_reg <= True;
-`endif
+// `endif
        execute_redirect_count <= execute_redirect_count + 1;
    endmethod

@@ -1222,11 +1222,11 @@ module mkFetchStage(FetchStage);

    interface Perf perf;
        method Action setStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            doStats <= stats;
-`else
-            noAction;
-`endif
+// `else
+//             noAction;
+// `endif
        endmethod

        method Action req(DecStagePerfType r);
@@ -1234,26 +1234,26 @@ module mkFetchStage(FetchStage);
        endmethod

        method ActionValue#(PerfResp#(DecStagePerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        method Bool respValid = perfRespQ.notEmpty;
-`else
-        method Bool respValid = perfReqQ.notEmpty;
-`endif
+// `else
+//         method Bool respValid = perfReqQ.notEmpty;
+// `endif
    endinterface

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method Bool redirect_evt = redirect_evt_reg._read;
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
@@ -172,13 +172,13 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
    FpuExec fpuExec <- mkFpuExecPipeline;

    // fpu/mul/div performance counters
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Count#(Data) exeIntMulCnt <- mkCount(0);
    Count#(Data) exeIntDivCnt <- mkCount(0);
    Count#(Data) exeFpFmaCnt <- mkCount(0);
    Count#(Data) exeFpDivCnt <- mkCount(0);
    Count#(Data) exeFpSqrtCnt <- mkCount(0);
-`endif
+// `endif

    rule doDispatchFpuMulDiv;
        rsFpuMulDiv.doDispatch;
@@ -345,11 +345,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
 `else
        doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags);
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeFpFmaCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    rule doFinishFpDiv;
@@ -360,11 +360,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
 `else
        doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags);
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeFpDivCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    rule doFinishFpSqrt;
@@ -375,11 +375,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
 `else
        doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags);
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeFpSqrtCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    rule doFinishIntMul;
@@ -390,11 +390,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
 `else
        doFinish(resp.dst, resp.tag, resp.data, 0);
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeIntMulCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    rule doFinishIntDiv;
@@ -405,11 +405,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
 `else
        doFinish(resp.dst, resp.tag, resp.data, 0);
 `endif
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeIntDivCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    interface recvBypass = map(getRecvBypassDataIfc, bypassWire);
@@ -426,13 +426,13 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);

    method Data getPerf(ExeStagePerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            ExeIntMulCnt: exeIntMulCnt;
            ExeIntDivCnt: exeIntDivCnt;
            ExeFpFmaCnt: exeFpFmaCnt;
            ExeFpDivCnt: exeFpDivCnt;
            ExeFpSqrtCnt: exeFpSqrtCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -75,12 +75,12 @@ import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
 import CacheUtils::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import BlueUtils::*;
 import StatCounters::*;
 import DReg::*;
-`endif
+// `endif

 import Cur_Cycle :: *;

@@ -241,12 +241,12 @@ interface MemExeInput;
    // performance
    method Bool doStats;

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
    method CapMem rob_getPredPC(InstTag t);
    method Bit #(32) rob_getOrig_Inst (InstTag t);
 `endif
-`endif
+// `endif
 endinterface

 interface MemExePipeline;
@@ -262,12 +262,12 @@ interface MemExePipeline;
    interface Server#(void, void) reconcile;
 `endif
    method Data getPerf(ExeStagePerfType t);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsCore events;
 `ifdef CONTRACTS_VERIFY
    method EventsTransExe events_trans;
 `endif
-`endif
+// `endif
 endinterface

 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
@@ -281,7 +281,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
    // These are always included as they are used by both stat counter systems.
    LatencyTimer#(LdQSize, 10) ldMemLatTimer <- mkLatencyTimer;
    LatencyTimer#(SBSize, 10) stMemLatTimer <- mkLatencyTimer;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    // load issue stall
    Count#(Data) exeLdStallByLdCnt <- mkCount(0);
    Count#(Data) exeLdStallByStCnt <- mkCount(0);
@@ -305,14 +305,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
    Count#(Data) exeFenceCnt <- mkCount(0);
    Count#(Data) exeFenceAcqCnt <- mkCount(0);
    Count#(Data) exeFenceRelCnt <- mkCount(0);
-`endif
+// `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsCore)) events_reg <- mkDRegOR (5, unpack (0));
 `ifdef CONTRACTS_VERIFY
    Reg#(EventsTransExe) events_trans_reg <- mkDReg(unpack(0));
 `endif
-`endif
+// `endif

    // reservation station
    ReservationStationMem rsMem <- mkReservationStationMem;
@@ -376,17 +376,17 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            end
            // perf: load mem latency
            let lat <- ldMemLatTimer.done(tag);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                exeLdMemLat.incr(zeroExtend(lat));
            end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
            EventsCore events = unpack(0);
            events.evt_LOAD_WAIT = saturating_truncate(lat);
            events.evt_MEM_CAP_LOAD_TAG_SET = (d.tag) ? 1 : 0;
            events_reg[1] <= events;
-`endif
+// `endif
        endmethod
        method Action respLrScAmo(DProcReqId id, MemTaggedData d);
            respLrScAmoQ.enq(d);
@@ -404,17 +404,17 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            end
            // perf: store mem latency
            let lat <- stMemLatTimer.done(0);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                exeStMemLat.incr(zeroExtend(lat));
            end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
            EventsCore events = unpack(0);
            if (pack(waitSt.shiftedBE) == -1) events.evt_MEM_CAP_STORE = 1;
            events.evt_STORE_WAIT = saturating_truncate(lat);
            events_reg[2] <= events;
-`endif
+// `endif
            // now figure out the data to be written
            CLineMemDataByteEn be = replicate(replicate(False));
            Line data = unpack(0);
@@ -431,17 +431,17 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            if(verbose) $display("[Store resp] idx = %x, ", idx, fshow(e));
            // perf: store mem latency
            let lat <- stMemLatTimer.done(idx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(inIfc.doStats) begin
                exeStMemLat.incr(zeroExtend(lat));
            end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
            EventsCore events = unpack(0);
            if (pack(e.byteEn) == -1) events.evt_MEM_CAP_STORE = 1;
            events.evt_STORE_WAIT = saturating_truncate(lat);
            events_reg[2] <= events;
-`endif
+// `endif
            return tuple2(unpack(pack(e.byteEn)), e.line); // return SB entry
        endmethod
 `endif
@@ -503,12 +503,12 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            spec_bits: x.spec_bits
        });

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // perf: load to use latency
        if(x.data.ldstq_tag matches tagged Ld .idx) begin
            ldToUseLatTimer.start(idx);
        end
-`endif
+// `endif
    endrule

 `ifdef RVFI
@@ -564,11 +564,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
        if(x.ldstq_tag matches tagged St .stTag) begin
            MemTaggedData d = x.mem_func == Amo ? toMemData : shiftData; // XXX don't shift for AMO
            lsq.updateData(stTag, d);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
            EventsCore events = unpack(0);
            events.evt_MEM_CAP_STORE_TAG_SET = (d.tag) ? 1 : 0;
            events_reg[4] <= events;
-`endif
+// `endif
        end

 `ifdef KONATA 
@@ -744,7 +744,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                                         );

        let pc = inIfc.rob_getPC(x.tag);
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        function Bool is_16b_inst (Bit #(n) inst);
            return (inst [1:0] != 2'b11);
@@ -758,7 +758,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            events_trans_reg <= events_trans;
        end
 `endif
-`endif
+// `endif

 `ifdef KONATA 
        $display("KONATAE\t%0d\t%0d\t0\tMem3", cur_cycle, x.u_id);
@@ -795,11 +795,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            });
        end

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(isValid(cause) && inIfc.doStats) begin
            exeTlbExcepCnt.incr(1);
        end
-`endif
+// `endif
    endrule

    //=======================================================
@@ -822,10 +822,10 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
 `else
        SBSearchRes sbRes = stb.search(info.paddr, info.shiftedBE);
 `endif
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        EventsCore events = unpack(0);
        if (info.shiftedBE == DataMemAccess (unpack(~0))) events.evt_MEM_CAP_LOAD = 1;
-`endif
+// `endif
        // search LSQ
        LSQIssueLdResult issRes <- lsq.issueLd(info.tag, info.paddr, info.shiftedBE, sbRes);
        if(verbose) begin
@@ -839,12 +839,12 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            if(forward.dst matches tagged Valid .dst) begin
                inIfc.setRegReadyAggr_forward(dst.indx);
            end
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // perf: load forward
            if(inIfc.doStats) begin
                exeLdForwardCnt.incr(1);
            end
-`endif
+// `endif
        end
        else if(issRes == ToCache) begin
            reqLdQ.enq(tuple4(zeroExtend(info.tag), info.paddr, info.shiftedBE == TagMemAccess, info.pcHash));
@@ -852,7 +852,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            ldMemLatTimer.start(info.tag);
        end
        else if(issRes matches tagged Stall .stallBy) begin
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // perf: load stall
            if(inIfc.doStats) begin
                case(stallBy)
@@ -862,14 +862,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                    default: doAssert(False, "unknow stall reason");
                endcase
            end
-`endif
+// `endif
        end
        else begin
            doAssert(False, "load is stalled");
        end
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        events_reg[0] <= events;
-`endif
+// `endif
    endaction
    endfunction

@@ -911,14 +911,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            inIfc.rob_setExecuted_doFinishMem_RegData (res.instTag, res.data);
 `endif

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // perf: load to use latency
            let lat <- ldToUseLatTimer.done(tag);
            if(inIfc.doStats) begin
                exeLdToUseLat.incr(zeroExtend(lat));
                exeLdToUseCnt.incr(1);
            end
-`endif
+// `endif
 `ifdef RVFI
            LdStQTag idx = tagged Ld tag;
            memData[pack(idx)] <= truncate(pack(res.data)); // TODO use fromMem?
@@ -1029,7 +1029,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
        if(verbose) $display("[doDeqLdQ_Lr_issue] ", fshow(lsqDeqLd), "; ", fshow(req));
        // check
        doAssert(!isValid(lsqDeqLd.killed), "cannot be killed");
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            if(lsqDeqLd.acq) begin
                exeLrScAmoAcqCnt.incr(1);
@@ -1038,7 +1038,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                exeLrScAmoRelCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

 `ifdef SELF_INV_CACHE
@@ -1320,7 +1320,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
 `endif
        );
        if(verbose) $display("[doDeqStQ_Fence] ", fshow(lsqDeqSt));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            exeFenceCnt.incr(1);
            if(lsqDeqSt.acq) begin
@@ -1330,7 +1330,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                exeFenceRelCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    // issue non-MMIO Sc/Amo without fault when
@@ -1373,7 +1373,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
        };
        reqLrScAmoQ.enq(req);
        if(verbose) $display("[doDeqStQ_ScAmo_issue] ", fshow(lsqDeqSt), "; ", fshow(req));
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            if(lsqDeqSt.acq) begin
                exeLrScAmoAcqCnt.incr(1);
@@ -1382,7 +1382,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                exeLrScAmoRelCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

 `ifdef SELF_INV_CACHE
@@ -1435,16 +1435,16 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                 !lsqDeqSt.isMMIO, "must be non-MMIO Sc/Amo");
        doAssert(!isValid(lsqDeqSt.fault), "no fault");
        // stats for successful SC
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats && lsqDeqSt.memFunc == Sc && resp == fromInteger(valueof(ScSuccVal))) begin
            exeScSuccessCnt.incr(1);
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsCore events = unpack(0);
        events.evt_SC_SUCCESS = 1;
        events_reg[3] <= events;
-`endif
+// `endif
    endrule

    // issue MMIO St/Amo when
@@ -1482,7 +1482,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
        if(verbose) $display("[doDeqStQ_MMIO_issue] ", fshow(lsqDeqSt), "; ", fshow(req));
        // MMIO may cause exception, must have spec tag, and only can be St/Amo
        doAssert(lsqDeqSt.memFunc == St || lsqDeqSt.memFunc == Amo, "must be St/Amo");
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            if(lsqDeqSt.acq) begin
                exeLrScAmoAcqCnt.incr(1);
@@ -1491,7 +1491,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
                exeLrScAmoRelCnt.incr(1);
            end
        end
-`endif
+// `endif
    endrule

 `ifdef SELF_INV_CACHE
@@ -1661,7 +1661,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);

    method Data getPerf(ExeStagePerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            ExeLdStallByLd: exeLdStallByLdCnt;
            ExeLdStallBySt: exeLdStallByStCnt;
            ExeLdStallBySB: exeLdStallBySBCnt;
@@ -1677,14 +1677,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
            ExeFenceAcqCnt: exeFenceAcqCnt;
            ExeFenceRelCnt: exeFenceRelCnt;
            ExeFenceCnt: exeFenceCnt;
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method events = events_reg[0];
 `ifdef CONTRACTS_VERIFY
    method events_trans = events_trans_reg;
 `endif
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -73,10 +73,10 @@ import ConfigReg::*;
 import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
 import DReg::*;
-`endif
+// `endif

 import Cur_Cycle :: *;

@@ -116,9 +116,9 @@ interface RenameStage;
    // performance count
    method Data getPerf(ExeStagePerfType t);

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsTransExe events;
-`endif
+// `endif

    // deadlock check
    interface Get#(RenameStuck) renameInstStuck;
@@ -150,15 +150,15 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);

    // performance counter
    Count#(Data) supRenameCnt <- mkCount(0);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
 `ifdef SECURITY
    Count#(Data) specNoneCycles <- mkCount(0);
    Count#(Data) specNonMemCycles <- mkCount(0);
 `endif
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Reg#(EventsTransExe) events_reg <- mkDReg(unpack(0));
-`endif
+// `endif
    // deadlock check
 `ifdef CHECK_DEADLOCK
    // timer to check deadlock
@@ -421,7 +421,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
        end
 `endif

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 `ifdef CONTRACTS_VERIFY
        let validPc = (x.orig_inst[1:0] != 2'b11) ? addPc(pc,2) : addPc(pc,4);
        if((ppc != validPc)) begin
@@ -430,7 +430,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
            events_reg <= events;
        end
 `endif
-`endif
+// `endif

 `ifdef CHECK_DEADLOCK
        renameCorrectPath.send;
@@ -636,11 +636,11 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
        $display("KONATAS\t%0d\t%d\t0\tRnm", cur_cycle, x.u_id);
        $fflush;
 `endif
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        EventsTransExe events = unpack(0);
        events.evt_RENAMED_INST = 1;
        events_reg <= events;
-`endif
+// `endif

        // record if we issue an CSR inst. TODO also for SCRs?
        if(dInst.iType == Csr) begin
@@ -660,14 +660,14 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
    Bool specNone = !machineMode && csrf.rd(csrAddrMSPEC) == zeroExtend(mSpecNone);
    Bool specNonMem = machineMode || csrf.rd(csrAddrMSPEC) == zeroExtend(mSpecNonMem);

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    rule incSpecNoneCycles(inIfc.doStats && specNone);
        specNoneCycles.incr(1);
    endrule
    rule incSpecNonMemCycles(inIfc.doStats && specNonMem);
        specNonMemCycles.incr(1);
    endrule
-`endif
+// `endif

    // first inst is mem inst
    function Bool isMemInst(ExecFunc f);
@@ -1251,20 +1251,20 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
        // otherwise this rule may block other rules forever
        when(doCorrectPath, noAction);

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(inIfc.doStats) begin
            if(renameCnt > 1) begin
                supRenameCnt.incr(1);
            end
        end
-`else
-        supRenameCnt.incr(zeroExtend(renameCnt));
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `else
+//         supRenameCnt.incr(zeroExtend(renameCnt));
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsTransExe events = unpack(0);
        events.evt_RENAMED_INST = zeroExtend(renameCnt);
        events_reg <= events;
-`endif
+// `endif

 `ifdef CHECK_DEADLOCK
        if(doCorrectPath) begin
@@ -1284,20 +1284,20 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);

    method Data getPerf(ExeStagePerfType t);
        return (case(t)
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            SupRenameCnt: supRenameCnt;
 `ifdef SECURITY
            SpecNoneCycles: specNoneCycles;
            SpecNonMemCycles: specNoneCycles;
 `endif
-`endif
+// `endif
            default: 0;
        endcase);
    endmethod

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method events = events_reg;
-`endif
+// `endif

 `ifdef INCLUDE_GDB_CONTROL
   method Action debug_halt_req ();
--- a/src_Core/RISCY_OOO/procs/lib/DTlb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/DTlb.bsv
@@ -52,12 +52,12 @@ import LatencyTimer::*;
 import HasSpecBits::*;
 import Vector::*;
 import Ehr::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import CCTypes::*;
 import BlueUtils::*;
 import StatCounters::*;
-`endif
+// `endif

 export DTlbReq(..);
 export DTlbResp(..);
@@ -123,9 +123,9 @@ interface DTlb#(type instT);

    // performance
    interface Perf#(L1TlbPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events;
-`endif
+// `endif
 endinterface

 typedef FullAssocTlb#(DTlbSize) DTlbArray;
@@ -210,7 +210,7 @@ module mkDTlb#(
    // perf counters
    LatencyTimer#(DTlbReqNum, 12) latTimer <- mkLatencyTimer; // max latency: 4K cycles
    Fifo#(1, L1TlbPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(L1TlbPerfType)) perfRespQ <- mkCFFifo;
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) accessCnt <- mkCount(0);
@@ -242,11 +242,12 @@ module mkDTlb#(
    rule incrAllMissCycles(doStats);
        function Bool isMiss(DTlbWait x) = x != None;
        when(all(isMiss, readVReg(pendWait)), allMissCycles.incr(1));
+        $display("L1TlballMissCycles = %0d", allMissCycles);
    endrule
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsL1D)) perf_events <- mkDRegOR (3, unpack (0));
-`endif
+// `endif

    // do flush: start when all misses resolve
    Bool noMiss = all(\== (False) , readVReg(pendValid_noMiss));
@@ -257,11 +258,11 @@ module mkDTlb#(
        flushRqToPQ.enq(?);
        waitFlushP <= True;
        if(verbose) $display("[DTLB] flush begin");
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        EventsL1D ev = unpack(0);
        ev.evt_TLB_FLUSH = 1;
        perf_events[2] <= ev;
-`endif
+// `endif
    endrule

    rule doFinishFlush(needFlush && waitFlushP);
@@ -357,24 +358,28 @@ module mkDTlb#(

        // perf: miss
        let lat <- latTimer.done(idx);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            if(isValid(respForOtherReq)) begin
                missPeerLat.incr(zeroExtend(lat));
+                $display("L1 TLB miss");
+                $display("L1TLBmissPeerLat = %0d", missPeerLat);
                missPeerCnt.incr(1);
            end
            else begin
                missParentLat.incr(zeroExtend(lat));
                missParentCnt.incr(1);
+                $display("L1 TLB parent miss");
+                $display("L1TLBmissParentCnt = %0d", missParentCnt);
            end
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsL1D ev = unpack(0);
        ev.evt_TLB_MISS_LAT = saturating_truncate(lat);
        ev.evt_TLB_MISS = 1;
        perf_events[0] <= ev;
-`endif
+// `endif
        // conflict with wrong spec
        wrongSpec_doPRs_conflict.wset(?);
    endrule
@@ -508,12 +513,13 @@ module mkDTlb#(
                        $display("[DTLB] req (hit): idx %d; ", idx, fshow(r),
                                 "; ", fshow(trans_result));
                    end
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                    // perf: hit under miss
                    if(doStats && readVReg(pendWait) != replicate(None)) begin
                        hitUnderMissCnt.incr(1);
+                        $display("L1TlbhitUnderMissCnt = %0d", hitUnderMissCnt);
                    end
-`endif
+// `endif
                end
                else begin
                    // page fault
@@ -565,17 +571,18 @@ module mkDTlb#(
            if(verbose) $display("DTLB %m req (bare): ", fshow(r));
        end

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // perf: access
        if(doStats) begin
+            $display("L1 TLB inc");
            accessCnt.incr(1);
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsL1D ev = unpack(0);
        ev.evt_TLB = 1;
        perf_events[1] <= ev;
-`endif
+// `endif
        // conflict with wrong spec
        wrongSpec_procReq_conflict.wset(?);
    endmethod
@@ -632,11 +639,11 @@ module mkDTlb#(

    interface Perf perf;
        method Action setStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            doStats <= stats;
-`else
-            noAction;
-`endif
+// `else
+//             noAction;
+// `endif
        endmethod

        method Action req(L1TlbPerfType r);
@@ -644,27 +651,27 @@ module mkDTlb#(
        endmethod

        method ActionValue#(PerfResp#(L1TlbPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod

        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events = perf_events[0];
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/lib/ITlb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ITlb.bsv
@@ -50,12 +50,12 @@ import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;
 import LatencyTimer::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import CCTypes::*;
 import BlueUtils::*;
 import StatCounters::*;
-`endif
+// `endif

 // currently blocking
 typedef `L1_TLB_SIZE ITlbSize;
@@ -92,9 +92,9 @@ interface ITlb;

    // performance
    interface Perf#(L1TlbPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events;
-`endif
+// `endif
 endinterface

 typedef FullAssocTlb#(ITlbSize) ITlbArray;
@@ -134,7 +134,7 @@ module mkITlb(ITlb::ITlb);
    // perf counters
    LatencyTimer#(2, 12) latTimer <- mkLatencyTimer; // max latency: 4K cycles
    Fifo#(1, L1TlbPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(L1TlbPerfType)) perfRespQ <- mkCFFifo;
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) accessCnt <- mkCount(0);
@@ -154,10 +154,10 @@ module mkITlb(ITlb::ITlb);
            data: d
        });
    endrule
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsL1I)) perf_events <- mkDRegOR (3, unpack (0));
-`endif
+// `endif

    // do flush: only start when all misses resolve
    rule doStartFlush(needFlush && !waitFlushP && !isValid(miss));
@@ -166,11 +166,11 @@ module mkITlb(ITlb::ITlb);
        flushRqToPQ.enq(?);
        waitFlushP <= True;
        if(verbose) $display("ITLB %m: flush begin");
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        EventsL1I ev = unpack(0);
        ev.evt_TLB_FLUSH = 1;
        perf_events[2] <= ev;
-`endif
+// `endif
    endrule

    rule doFinishFlush(needFlush && waitFlushP && !isValid(miss));
@@ -225,17 +225,17 @@ module mkITlb(ITlb::ITlb);
        miss <= Invalid;

        let lat <- latTimer.done(0);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        if(doStats) begin
            missLat.incr(zeroExtend(lat));
        end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
        EventsL1I ev = unpack(0);
        ev.evt_TLB_MISS_LAT = saturating_truncate(lat);
        ev.evt_TLB_MISS = 1;
        perf_events[0] <= ev;
-`endif
+// `endif
    endrule

    // we check no pending req only at Commit when Fetch1 stage has been
@@ -345,11 +345,11 @@ module mkITlb(ITlb::ITlb);
                            $display("ITLB %m req (miss): ", fshow(vaddr));
                        end
                        latTimer.start(0);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                        if(doStats) begin
                            missCnt.incr(1);
                        end
-`endif
+// `endif
                    end
                end
                else begin
@@ -358,16 +358,16 @@ module mkITlb(ITlb::ITlb);
                    if (verbose) $display("ITLB %m req (bare): ", fshow(vaddr));
                end

-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                if(doStats) begin
                    accessCnt.incr(1);
                end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
                EventsL1I ev = unpack(0);
                ev.evt_TLB = 1;
                perf_events[1] <= ev;
-`endif
+// `endif
            endmethod
        endinterface
        interface Get response = toGet(hitQ);
@@ -384,11 +384,11 @@ module mkITlb(ITlb::ITlb);

    interface Perf perf;
        method Action setStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            doStats <= stats;
-`else
-            noAction;
-`endif
+// `else
+//             noAction;
+// `endif
        endmethod

        method Action req(L1TlbPerfType r);
@@ -396,27 +396,27 @@ module mkITlb(ITlb::ITlb);
        endmethod

        method ActionValue#(PerfResp#(L1TlbPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod

        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events = perf_events[0];
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
@@ -59,9 +59,9 @@ import SelfInvL1Pipe::*;
 import SelfInvL1Bank::*;
 import SelfInvIPipe::*;
 import SelfInvIBank::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 export L1Num;
 export LgL1WayNum;
@@ -188,9 +188,9 @@ interface DCoCache;
    method Bool flush_done;
    method Action resetLinkAddr;
    interface Perf#(L1DPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events;
-`endif
+// `endif

    interface ChildCacheToParent#(L1Way, void) to_parent;

@@ -208,7 +208,7 @@ module mkDCoCache#(L1ProcResp#(DProcReqId) procResp)(DCoCache);

    // perf counters
    Fifo#(1, L1DPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(L1DPerfType)) perfRespQ <- mkCFFifo;

    rule doPerf;
@@ -219,7 +219,7 @@ module mkDCoCache#(L1ProcResp#(DProcReqId) procResp)(DCoCache);
            data: d
        });
    endrule
-`endif
+// `endif

 `ifdef SELF_INV_CACHE
    // change the reconcile ifc to a FIFO ifc to avoid scheduling issues
@@ -261,28 +261,28 @@ module mkDCoCache#(L1ProcResp#(DProcReqId) procResp)(DCoCache);
            perfReqQ.enq(r);
        endmethod
        method ActionValue#(PerfResp#(L1DPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod
        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1D events = cache.events;
-`endif
+// `endif

    interface to_parent = cache.to_parent;

@@ -382,9 +382,9 @@ interface ICoCache;
    method Action flush;
    method Bool flush_done;
    interface Perf#(L1IPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events;
-`endif
+// `endif

    interface ChildCacheToParent#(L1Way, void) to_parent;

@@ -407,7 +407,7 @@ module mkICoCache(ICoCache);
    let cache <- mkIBankWrapper;

    Fifo#(1, L1IPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(L1IPerfType)) perfRespQ <- mkCFFifo;

    rule doPerf;
@@ -418,7 +418,7 @@ module mkICoCache(ICoCache);
            data: d
        });
    endrule
-`endif
+// `endif

    interface Server to_proc;
        interface request = cache.to_proc.req;
@@ -436,28 +436,28 @@ module mkICoCache(ICoCache);
            perfReqQ.enq(r);
        endmethod
        method ActionValue#(PerfResp#(L1IPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod
        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsL1I events = cache.events;
-`endif
+// `endif

    interface to_parent = cache.to_parent;

--- a/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
@@ -54,12 +54,12 @@ import SetAssocTlb::*;
 import L2SetAssocTlb::*;
 import TranslationCache::*;
 import LatencyTimer::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import PerformanceMonitor::*;
 import CCTypes::*;
 import BlueUtils::*;
 import StatCounters::*;
-`endif
+// `endif

 // for SV39 only

@@ -120,9 +120,9 @@ interface L2Tlb;

    // performace
    interface Perf#(L2TlbPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsLL events;
-`endif
+// `endif
 endinterface

 typedef FullAssocTlb#(`L2_TLB_HUGE_SIZE) L2FullAssocTlb;
@@ -220,7 +220,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);

    // FIFO for perf req
    Fifo#(1, L2TlbPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(L2TlbPerfType)) perfRespQ <- mkCFFifo;
    Reg#(Bool) doStats <- mkConfigReg(False);
    Count#(Data) instMissCnt <- mkCount(0);
@@ -285,10 +285,10 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            data: d
        });
    endrule
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
    Array #(Reg #(EventsLL)) perf_events <- mkDRegOR (3, unpack (0));
-`endif
+// `endif

    // when flushing is true, since both I and D TLBs have finished flush and
    // is waiting for L2 to flush, all I/D TLB req must have been responded.
@@ -301,11 +301,11 @@ module mkL2Tlb(L2Tlb::L2Tlb);
        // check no req
        doAssert(!rqFromCQ.notEmpty, "cannot have new req");
        doAssert(readVEhr(0, pendValid) == replicate(False), "cannot have pending req");
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
        EventsLL ev = unpack(0);
        ev.evt_TLB_FLUSH = 1;
        perf_events[2] <= ev;
-`endif
+// `endif
    endrule

    rule doWaitFlush(flushing && waitFlushDone && tlb4KB.flush_done && transCache.flush_done);
@@ -377,7 +377,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            });
            // req is done
            pendValid_tlbResp[idx] <= False;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // perf: hit under miss
            function Bool otherMiss(L2TlbReqIdx i);
                return pendValid_tlbResp[i] && pendWait_tlbResp[i] != None && i != idx;
@@ -386,7 +386,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            if(any(otherMiss, idxVec)) begin
                hitUnderMissCnt.incr(1);
            end
-`endif
+// `endif
        endaction
        endfunction

@@ -410,7 +410,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            pageHit(entry);
            tlb4KB.deqResp(Invalid); // just deq 4KB array
            tlbMG.updateRepByHit(respMG.index); // update replacement in MG array
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(doStats) begin
                if(cRq.child == I) begin
                    instHugePageHitCnt.incr(1);
@@ -419,12 +419,12 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                    dataHugePageHitCnt.incr(1);
                end
            end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
            EventsLL ev = unpack(0);
            ev.evt_TLB = 1;
            perf_events[1] <= ev;
-`endif
+// `endif
        end
        else if(resp4KB.hit) begin
            // hit on 4KB page
@@ -433,11 +433,11 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            pageHit(entry);
            // update 4KB array replacement, no need to touch MG array
            tlb4KB.deqResp(Valid (resp4KB.way));
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
            EventsLL ev = unpack(0);
            ev.evt_TLB = 1;
            perf_events[1] <= ev;
-`endif
+// `endif
        end
        else begin
            // miss, deq resp
@@ -446,7 +446,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            transCache.req(cRq.vpn, vm_info.asid);
            transCacheReqQ.enq(idx);
            // perf: TLB miss
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            latTimer.start(idx);
            if(doStats) begin
                if(cRq.child == I) begin
@@ -456,12 +456,12 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                    dataMissCnt.incr(1);
                end
            end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
            EventsLL ev = unpack(0);
            ev.evt_TLB_MISS = 1;
            perf_events[0] <= ev;
-`endif
+// `endif
        end
    endrule

@@ -517,11 +517,11 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            // duplicate req
            pendWait_transCacheResp[idx] <= WaitPeer (i);
            doAssert(pendValid_transCacheResp[i], "peer must be valid");
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            if(doStats) begin
                peerSavedMemReqCnt.incr(1);
            end
-`endif
+// `endif
        end
        else begin
            // no one has requested before, req memory
@@ -536,7 +536,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                     fshow(vm_info), "; ", fshow(resp), "; ",
                     fshow(level), "; ", fshow(pteAddr));
        end
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // perf: saved page walks
        if(doStats) begin
            Data saved = zeroExtend(maxPageWalkLevel - level);
@@ -547,7 +547,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                dataSavedPageWalks.incr(saved);
            end
        end
-`endif
+// `endif
    endrule

    // page walk is preempted by tlb resp rule and trans cache resp rule, i.e.,
@@ -588,10 +588,10 @@ module mkL2Tlb(L2Tlb::L2Tlb);
            // req is done
            pendValid_pageWalk[idx] <= False;
            pendWait_pageWalk[idx] <= None;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            // incr miss latency
            incrMissLat(cRq.child, idx);
-`endif
+// `endif
        endaction
        endfunction

@@ -656,11 +656,11 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                    // walk 
                    if(otherReqSamePTE(idx, newPTEAddr, readVReg(pendWait_pageWalk)) matches tagged Valid .i) begin
                        pendWait_pageWalk[idx] <= WaitPeer (i);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                        if(doStats) begin
                            peerSavedMemReqCnt.incr(1);
                        end
-`endif
+// `endif
                    end
                    else begin
                        memReqQ.enq(TlbMemReq {
@@ -695,17 +695,17 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                    child: cRq.child,
                    entry: Valid (entry)
                });
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
                // page table walks are counted as accesses
                EventsLL ev = unpack(0);
                ev.evt_TLB = 1;
                perf_events[1] <= ev;
-`endif
+// `endif
                // update TLB array
                if(entry.level > 0) begin
                    // add to mega/giga page tlb
                    tlbMG.addEntry(entry);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                    if(doStats) begin
                        if(cRq.child == I) begin
                            instHugePageMissCnt.incr(1);
@@ -714,12 +714,12 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                            dataHugePageMissCnt.incr(1);
                        end
                    end
-`endif
-`ifdef PERFORMANCE_MONITORING
+// `endif
+// `ifdef PERFORMANCE_MONITORING
                    EventsLL ev = unpack(0);
                    ev.evt_TLB_MISS = 1;
                    perf_events[0] <= ev;
-`endif
+// `endif
                end
                else begin
                    // 4KB page, add to 4KB TLB
@@ -728,13 +728,13 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                // req is done
                pendValid_pageWalk[idx] <= False;
                pendWait_pageWalk[idx] <= None;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
                // incr miss latency
                incrMissLat(cRq.child, idx);
-`endif
+// `endif
            end
        end
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
        // perf: page walk done once
        if(doStats) begin
            if(cRq.child == I) begin
@@ -744,7 +744,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                dataPageWalks.incr(1);
            end
        end
-`endif
+// `endif
    endrule

    method Action updateVMInfo(VMInfo vmI, VMInfo vmD); //if(!isValid(pendReq));
@@ -776,11 +776,11 @@ module mkL2Tlb(L2Tlb::L2Tlb);
  
    interface Perf perf;
        method Action setStatus(Bool stats);
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            doStats <= stats;
-`else
-            noAction;
-`endif
+// `else
+//             noAction;
+// `endif
        endmethod

        method Action req(L2TlbPerfType r);
@@ -788,27 +788,27 @@ module mkL2Tlb(L2Tlb::L2Tlb);
        endmethod

        method ActionValue#(PerfResp#(L2TlbPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod

        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsLL events = perf_events[0];
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/lib/LLCache.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/LLCache.bsv
@@ -55,9 +55,9 @@ import SelfInvLLBank::*;
 import L1CoCache::*;
 import LLCDmaConnect::*;
 import Performance::*;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 import StatCounters::*;
-`endif
+// `endif

 // Last-Level

@@ -257,9 +257,9 @@ interface LLCache;
    interface Get#(LLCStuck) cRqStuck;
    // performance
    interface Perf#(LLCPerfType) perf;
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsLL events;
-`endif
+// `endif
 endinterface

 `ifdef SECURITY
@@ -315,7 +315,7 @@ module mkLLCache(LLCache);

    // perf counters
    Fifo#(1, LLCPerfType) perfReqQ <- mkCFFifo;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
    Fifo#(1, PerfResp#(LLCPerfType)) perfRespQ <- mkCFFifo;

    rule doPerf;
@@ -326,7 +326,7 @@ module mkLLCache(LLCache);
            data: d
        });
    endrule
-`endif
+// `endif

 `ifdef SECURITY
 `ifndef DISABLE_SECURE_LLC
@@ -449,26 +449,26 @@ module mkLLCache(LLCache);
            perfReqQ.enq(r);
        endmethod
        method ActionValue#(PerfResp#(LLCPerfType)) resp;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            perfRespQ.deq;
            return perfRespQ.first;
-`else
-            perfReqQ.deq;
-            return PerfResp {
-                pType: perfReqQ.first,
-                data: 0
-            };
-`endif
+// `else
+//             perfReqQ.deq;
+//             return PerfResp {
+//                 pType: perfReqQ.first,
+//                 data: 0
+//             };
+// `endif
        endmethod
        method Bool respValid;
-`ifdef PERF_COUNT
+// `ifdef PERF_COUNT
            return perfRespQ.notEmpty;
-`else
-            return perfReqQ.notEmpty;
-`endif
+// `else
+//             return perfReqQ.notEmpty;
+// `endif
        endmethod
    endinterface
-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
    method EventsLL events = cache.events;
-`endif
+// `endif
 endmodule
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -1070,11 +1070,11 @@ endfunction

 function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));

-`ifdef PERFORMANCE_MONITORING
+// `ifdef PERFORMANCE_MONITORING
 typedef   8 Report_Width;
 typedef  64 Counter_Width;
 typedef  29 No_Of_Ctrs;
-`endif
+// `endif

 function Bit#(outWidth) hash(Bit#(inWidth) in)
    provisos(Add#(a__, inWidth, TMul#(TDiv#(inWidth, outWidth), outWidth)),
Author	SHA1	Message	Date
Akilan	0e8b7f38dc	l1 tlb performance metrics working	2026-04-09 13:31:59 +01:00
Akilan	af459956b7	enabled performance counters	2026-04-09 01:13:56 +01:00