145 lines
3.8 KiB
Python
145 lines
3.8 KiB
Python
def compute_percent_diff(regular, modified):
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percent_diff = {}
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for key in regular:
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if key in modified and regular[key] != 0:
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percent_diff[key] = ((regular[key] - modified[key]) / regular[key]) * 100
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return percent_diff
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def compute_percent_diff_mod_vs_pte(modified, after_pte):
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percent_diff = {}
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for key in ["CPU_cycles", "L1_DTLB_access"]:
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if key in modified and key in after_pte and modified[key] != 0:
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percent_diff[key] = ((modified[key] - after_pte[key]) / modified[key]) * 100
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return percent_diff
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performance_data = {
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"Mem": {
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"regular": {
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"CPU_cycles": 33940,
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"L1_DTLB_access": 13202,
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"L1_DTLB_miss": 36,
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"L2_DTLB_miss": 10,
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},
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"modified": {
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"CPU_cycles": 2457,
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"L1_DTLB_access": 151,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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"after_PTE_setup": {
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"CPU_cycles": 531,
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"L1_DTLB_access": 25,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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},
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"Test_C": {
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"regular": {
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"CPU_cycles": 34040,
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"L1_DTLB_access": 13284,
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"L1_DTLB_miss": 36,
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"L2_DTLB_miss": 10,
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},
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"modified": {
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"CPU_cycles": 2789,
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"L1_DTLB_access": 396,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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"after_PTE_setup": {
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"CPU_cycles": 631,
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"L1_DTLB_access": 107,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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},
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"Glibc": {
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"regular": {
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"CPU_cycles": 36053,
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"L1_DTLB_access": 14027,
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"L1_DTLB_miss": 36,
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"L2_DTLB_miss": 10,
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},
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"modified": {
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"CPU_cycles": 4219,
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"L1_DTLB_access": 783,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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"after_PTE_setup": {
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"CPU_cycles": 2644,
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"L1_DTLB_access": 850,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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},
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"Setup": {
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"regular": {
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"CPU_cycles": 33409,
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"L1_DTLB_access": 13177,
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"L1_DTLB_miss": 36,
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"L2_DTLB_miss": 10,
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}
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},
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"Richards": {
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"regular": {
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"CPU_cycles": 37808,
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"L1_DTLB_access": 14363,
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"L1_DTLB_miss": 10,
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"L2_DTLB_miss": 6,
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},
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"modified": {
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"CPU_cycles": 4433,
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"L1_DTLB_access": 874,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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"after_PTE_setup": {
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"CPU_cycles": 4399,
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"L1_DTLB_access": 1186,
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},
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},
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"Matrix_mul": {
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"regular": {
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"CPU_cycles": 42383,
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"L1_DTLB_access": 17020,
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"L1_DTLB_miss": 14,
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"L2_DTLB_miss": 10,
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},
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"modified": {
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"CPU_cycles": 12149,
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"L1_DTLB_access": 4411,
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"L1_DTLB_miss": 0,
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"L2_DTLB_miss": 0,
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},
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"after_PTE_setup": {
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"CPU_cycles": 8974,
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"L1_DTLB_access": 3843,
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},
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}
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}
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# Add percentage differences
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for test, data in performance_data.items():
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if "regular" in data and "modified" in data:
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data["percent_diff"] = compute_percent_diff(
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data["regular"], data["modified"]
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)
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# Add modified vs after_PTE_setup percentage differences
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for test, data in performance_data.items():
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if "modified" in data and "after_PTE_setup" in data:
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data["mod_vs_pte_percent_diff"] = compute_percent_diff_mod_vs_pte(
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data["modified"], data["after_PTE_setup"]
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)
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# Example usage:
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print(performance_data["Mem"]["percent_diff"])
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print(performance_data["Mem"]["mod_vs_pte_percent_diff"]) |