Peter Rugg 1cfc58c2cc Fix debug module reset state machine ...

dmactive should only go low when the debug module has successfully
reset. Approximate this by waiting for 1024 cycles, allowing any
register access requests and system bus requests to come back.

2024-09-16 23:15:24 +01:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Revert "Use only 20 bits of address on the AXI lite port"

2024-09-11 20:02:35 +01:00

CPU

Return Abstract Command Error on unsupported CSRs

2024-09-16 18:45:19 +01:00

Debug_Module

Fix debug module reset state machine

2024-09-16 23:15:24 +01:00

ISA

Cleanup unused exception code

2023-06-20 16:46:39 +01:00

PLIC

Changes to build with a 512-bit main data bus (with all other busses

2022-11-11 17:52:32 +00:00

RISCY_OOO

Return Abstract Command Error on unsupported CSRs

2024-09-16 18:45:19 +01:00