100 lines
5.5 KiB
Markdown
100 lines
5.5 KiB
Markdown
# Performance Monitoring Module
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**PLEASE NOTE: THIS DOCUMENT IS DEPRECATED AND ONLY EXISTS FOR A PERIOD OF TRANSITION**. For the current mapping, see [here](https://github.com/CTSRD-CHERI/RISCV_HPM_Events/blob/master/counters.yaml).
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This overview is based on this [document](https://github.com/CTSRD-CHERI/Flute/blob/CHERI/Doc/Performance_Monitor/Performance_Monitoring.md).
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## Usage
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To use the module, enable `PERFORMANCE_MONITORING` in your build (ensure that `BSC_COMPILATION_FLAGS` includes `-D PERFORMANCE_MONITORING` when running make).
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Code running on a core with `PERFORMANCE_MONITORING` enabled can now access any of the relevant counter CSRs as specified by the [RISC-V Privileged Specification](https://riscv.org/technical/specifications/) (section __3.1.11 Hardware Performance Monitor__).
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The implemented CSRs are:
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- `mcycle` and `minstret` (also work without `PERFORMANCE_MONITORING` enabled)
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- `mhpmcounter3–mhpmcounter31` event counters (29 total)
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- `mcycleh`, `minstreth` & `mhpmcounternh` versions of the above to access the high bits on RV32
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- `cycle`, `instret` & `hpmcountern` as read-only shadows
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- `mhpmevent3-mhpmevent31` event selectors
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- `mcounteren` to enable reads to masked counters in S- and U-mode (Seems that check is implemented in CSR_RegFile, but never used)
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- `mcountinhibit` to control which counters increment
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- `scounteren` to enable reads to masked counters in U-mode
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## Events
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Any event happening any number of times per cycle in the core can be counted, using the provided `mhpmcounter<N>` and `mhpmevent<N>` CSRs. Most common events are already provided, though it should be simple to extend and add additional events as needed.
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The following events along with corresponding event id (this id should be written to the `mhpmevent<N>` selector CSR) are given:
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- No event (0x0)
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Core events:
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- Redirect – count PC redirects (0x1)
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- Traps – caused by a dmem exception or failed CHERI check (0x2)
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- Branch – count branch instrs (0x3)
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- Jal – count jal instrs (0x4)
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- Jalr – count jalr instrs (0x5)
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- Auipc – count auipc instrs (0x6)
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- Load – count load instrs (0x7)
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- Store – count store instrs (0x8)
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- LR – count lr instrs (0x9)
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- SC – count sc instrs (0xa)
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- AMO – count (non lr or sc) atomic instrs (0xb)
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- Serial shift – count serial shift (slli, srli, srai) instrs (0xc)
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- Integer Mult/Div – count integer multiply and divide instrs (0xd)
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- FP – count all floating point instrs (0xe)
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- SC Success – count SC successes (0xf)
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- Load wait – count cycles waiting on load (0x10)
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- Store wait – count cycles waiting on store (0x11)
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- Fence – count fence instrs (0x12)
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The following events are defined in Toooba, but not implemented (mostly due
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to the fact that they are Flute-only events)
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-------------------------------
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- F Busy No Consume – count cycles where stage F is busy (0x13)
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- D Busy No Consume – count cycles where stage F is ready to pipe but D is busy (0x14)
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- 1 Busy No Consume – count cycles where stage D is ready to pipe but 1 is busy (0x15)
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- 2 Busy No Consume – count cycles where stage 1 is ready to pipe but 2 is busy (0x16)
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- 3 Busy No Consume – count cycles where stage 2 is ready to pipe but 3 is busy (0x17)
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- Imprecise setbounds – count when a setbounds instr does NOT result in the exact bounds requested (0x18)
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- Unrepresentable cap – count when a capability is out of bounds (due to set offset instr) and is nullified (0x19)
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---------------------------------------------------
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- Mem cap load – count when capability wide data are loaded, regardless of tag (0x1a)
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- Mem cap store – count when capability wide data are loaded, regardless of tag (0x1b)
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- Mem cap load tag set – count when a tagged capability is loaded (0x1c)
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- Mem cap store tag set – count when stage a tagged capability is stored (0x1d)
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IMem, DMem L1 Cache, and LL Cache (including the respective TLBs); events identical for all three, though some are irrelevant for the respective caches. IDs in format (IMem/DMem/LLC):
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- Load – count loads requested by cpu (0x20/0x30/unimplemented)
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- Load miss – count loads missed (0x21/0x31/0x61)
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- Load miss latency – count cycles waiting on a load miss (0x22/0x32/0x62)
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- Store – count stores requested by cpu (unimplemented/0x33/unimplemented)
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- Store miss – (unimplemented/unimplemented/unimplemented)
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- Store miss latency – (unimplemented/unimplemented/unimplemented)
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- Amo – count atomic ops requested by cpu (unimplemented/0x36/unimplemented)
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- Amo miss – count atomics missed (unimplemented/0x37/unimplemented)
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- Amo miss latency – count cycles waiting on a atomics miss (unimplemented/0x38/unimplemented)
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- Tlb – count tlb accesses (0x29/0x39/0x69)
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- Tlb miss – count tlb missed (0x2a/0x3a/0x6a)
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- Tlb miss latency – count cycles waiting on a tlb miss (0x2b/0x3b/unimplemented)
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- Tlb flush – count tlb flushes (0x2c/0x3c/0x6c)
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- Evict – count cache line evictions (unimplemented/unimplemented/unimplemented)
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TagController events:
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- Write – count writes to tag cache (0x40)
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- Write miss (0x41)
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- Read (0x42)
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- Read miss (0x43)
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- Evict (0x44)
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- Set tag write (0x45)
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- Set tag read (0x46)
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Transient-execution events
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- Renamed Instructions – count renamed instructions excluding instructions that are already trapping (0x70)
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Missing events are:
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- L1 WT CHERI events
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- L1 WB events
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- L2 WB events
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- AXI4 events for CHERI-enabled builds
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- External events
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