Toooba/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v

//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Thu Jul 16 18:27:44 BST 2020
//
//
// Ports:
// Name                         I/O  size props
// m_plic_addr_range              O   128 const
// m_near_mem_io_addr_range       O   128 const
// m_flash_mem_addr_range         O   128 const
// m_ethernet_0_addr_range        O   128 const
// m_dma_0_addr_range             O   128 const
// m_uart16550_0_addr_range       O   128 const
// m_gpio_0_addr_range            O   128 const
// m_boot_rom_addr_range          O   128 const
// m_ddr4_0_uncached_addr_range   O   128 const
// m_ddr4_0_cached_addr_range     O   128 const
// m_mem0_controller_addr_range   O   128 const
// m_is_mem_addr                  O     1
// m_is_IO_addr                   O     1
// m_is_near_mem_IO_addr          O     1
// m_pc_reset_value               O    64 const
// m_mtvec_reset_value            O    64 const
// m_nmivec_reset_value           O    64
// CLK                            I     1 unused
// RST_N                          I     1 unused
// m_is_mem_addr_addr             I    64
// m_is_IO_addr_addr              I    64
// m_is_IO_addr_imem_not_dmem     I     1
// m_is_near_mem_IO_addr_addr     I    64
//
// Combinational paths from inputs to outputs:
//   m_is_mem_addr_addr -> m_is_mem_addr
//   (m_is_IO_addr_addr, m_is_IO_addr_imem_not_dmem) -> m_is_IO_addr
//   m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkSoC_Map(CLK,
		 RST_N,

		 m_plic_addr_range,

		 m_near_mem_io_addr_range,

		 m_flash_mem_addr_range,

		 m_ethernet_0_addr_range,

		 m_dma_0_addr_range,

		 m_uart16550_0_addr_range,

		 m_gpio_0_addr_range,

		 m_boot_rom_addr_range,

		 m_ddr4_0_uncached_addr_range,

		 m_ddr4_0_cached_addr_range,

		 m_mem0_controller_addr_range,

		 m_is_mem_addr_addr,
		 m_is_mem_addr,

		 m_is_IO_addr_addr,
		 m_is_IO_addr_imem_not_dmem,
		 m_is_IO_addr,

		 m_is_near_mem_IO_addr_addr,
		 m_is_near_mem_IO_addr,

		 m_pc_reset_value,

		 m_mtvec_reset_value,

		 m_nmivec_reset_value);
  input  CLK;
  input  RST_N;

  // value method m_plic_addr_range
  output [127 : 0] m_plic_addr_range;

  // value method m_near_mem_io_addr_range
  output [127 : 0] m_near_mem_io_addr_range;

  // value method m_flash_mem_addr_range
  output [127 : 0] m_flash_mem_addr_range;

  // value method m_ethernet_0_addr_range
  output [127 : 0] m_ethernet_0_addr_range;

  // value method m_dma_0_addr_range
  output [127 : 0] m_dma_0_addr_range;

  // value method m_uart16550_0_addr_range
  output [127 : 0] m_uart16550_0_addr_range;

  // value method m_gpio_0_addr_range
  output [127 : 0] m_gpio_0_addr_range;

  // value method m_boot_rom_addr_range
  output [127 : 0] m_boot_rom_addr_range;

  // value method m_ddr4_0_uncached_addr_range
  output [127 : 0] m_ddr4_0_uncached_addr_range;

  // value method m_ddr4_0_cached_addr_range
  output [127 : 0] m_ddr4_0_cached_addr_range;

  // value method m_mem0_controller_addr_range
  output [127 : 0] m_mem0_controller_addr_range;

  // value method m_is_mem_addr
  input  [63 : 0] m_is_mem_addr_addr;
  output m_is_mem_addr;

  // value method m_is_IO_addr
  input  [63 : 0] m_is_IO_addr_addr;
  input  m_is_IO_addr_imem_not_dmem;
  output m_is_IO_addr;

  // value method m_is_near_mem_IO_addr
  input  [63 : 0] m_is_near_mem_IO_addr_addr;
  output m_is_near_mem_IO_addr;

  // value method m_pc_reset_value
  output [63 : 0] m_pc_reset_value;

  // value method m_mtvec_reset_value
  output [63 : 0] m_mtvec_reset_value;

  // value method m_nmivec_reset_value
  output [63 : 0] m_nmivec_reset_value;

  // signals for module outputs
  wire [127 : 0] m_boot_rom_addr_range,
		 m_ddr4_0_cached_addr_range,
		 m_ddr4_0_uncached_addr_range,
		 m_dma_0_addr_range,
		 m_ethernet_0_addr_range,
		 m_flash_mem_addr_range,
		 m_gpio_0_addr_range,
		 m_mem0_controller_addr_range,
		 m_near_mem_io_addr_range,
		 m_plic_addr_range,
		 m_uart16550_0_addr_range;
  wire [63 : 0] m_mtvec_reset_value, m_nmivec_reset_value, m_pc_reset_value;
  wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr;

  // remaining internal signals
  wire [63 : 0] x__h181,
		x__h207,
		x__h231,
		x__h256,
		x__h282,
		x__h306,
		x__h331,
		x__h356,
		x__h381,
		x__h406,
		x__h660;
  wire NOT_m_is_IO_addr_addr_ULT_0x62300000_6___d47,
       NOT_m_is_IO_addr_addr_ULT_0x70000000_AND_m_is__ETC___d21,
       NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d39,
       NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d51,
       NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d70,
       NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d95,
       NOT_m_is_IO_addr_imem_not_dmem_2_AND_NOT_m_is__ETC___d99,
       m_is_IO_addr_addr_ULT_0x30000000___d93,
       m_is_IO_addr_addr_ULT_1073741824___d16;

  // value method m_plic_addr_range
  assign m_plic_addr_range = 128'h000000000C0000000000000000400000 ;

  // value method m_near_mem_io_addr_range
  assign m_near_mem_io_addr_range = 128'h00000000100000000000000000010000 ;

  // value method m_flash_mem_addr_range
  assign m_flash_mem_addr_range = 128'h00000000400000000000000008000000 ;

  // value method m_ethernet_0_addr_range
  assign m_ethernet_0_addr_range = 128'h00000000621000000000000000040000 ;

  // value method m_dma_0_addr_range
  assign m_dma_0_addr_range = 128'h00000000622000000000000000010000 ;

  // value method m_uart16550_0_addr_range
  assign m_uart16550_0_addr_range = 128'h00000000623000000000000000001000 ;

  // value method m_gpio_0_addr_range
  assign m_gpio_0_addr_range = 128'h000000006FFF00000000000000010000 ;

  // value method m_boot_rom_addr_range
  assign m_boot_rom_addr_range = 128'h00000000700000000000000000001000 ;

  // value method m_ddr4_0_uncached_addr_range
  assign m_ddr4_0_uncached_addr_range =
	     128'h00000000800000000000000040000000 ;

  // value method m_ddr4_0_cached_addr_range
  assign m_ddr4_0_cached_addr_range = 128'h00000000C00000000000000040000000 ;

  // value method m_mem0_controller_addr_range
  assign m_mem0_controller_addr_range =
	     128'h00000000C00000000000000040000000 ;

  // value method m_is_mem_addr
  assign m_is_mem_addr =
	     m_is_mem_addr_addr >= 64'h00000000C0000000 &&
	     x__h181 < 64'h0000000040000000 ;

  // value method m_is_IO_addr
  assign m_is_IO_addr =
	     NOT_m_is_IO_addr_addr_ULT_0x70000000_AND_m_is__ETC___d21 ||
	     NOT_m_is_IO_addr_imem_not_dmem_2_AND_NOT_m_is__ETC___d99 ;

  // value method m_is_near_mem_IO_addr
  assign m_is_near_mem_IO_addr =
	     m_is_near_mem_IO_addr_addr >= 64'h0000000010000000 &&
	     x__h660 < 64'h0000000000010000 ;

  // value method m_pc_reset_value
  assign m_pc_reset_value = 64'h0000000070000000 ;

  // value method m_mtvec_reset_value
  assign m_mtvec_reset_value = 64'h0000000000001000 ;

  // value method m_nmivec_reset_value
  assign m_nmivec_reset_value =
	     64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */  ;

  // remaining internal signals
  assign NOT_m_is_IO_addr_addr_ULT_0x62300000_6___d47 =
	     m_is_IO_addr_addr >= 64'h0000000062300000 ;
  assign NOT_m_is_IO_addr_addr_ULT_0x70000000_AND_m_is__ETC___d21 =
	     m_is_IO_addr_addr >= 64'h0000000070000000 &&
	     x__h207 < 64'h0000000000001000 ||
	     m_is_IO_addr_addr >= 64'h0000000080000000 &&
	     x__h231 < 64'h0000000040000000 ||
	     !m_is_IO_addr_addr_ULT_1073741824___d16 &&
	     x__h256 < 64'h0000000008000000 ;
  assign NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d39 =
	     m_is_IO_addr_addr >= 64'h000000000C000000 &&
	     x__h282 < 64'h0000000000400000 ||
	     m_is_IO_addr_addr >= 64'h0000000010000000 &&
	     x__h306 < 64'h0000000000010000 ||
	     m_is_IO_addr_addr >= 64'h0000000062100000 &&
	     x__h331 < 64'h0000000000040000 ;
  assign NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d51 =
	     NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d39 ||
	     m_is_IO_addr_addr >= 64'h0000000062200000 &&
	     x__h356 < 64'h0000000000010000 ||
	     NOT_m_is_IO_addr_addr_ULT_0x62300000_6___d47 &&
	     x__h381 < 64'h0000000000001000 ;
  assign NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d70 =
	     NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d51 ||
	     m_is_IO_addr_addr >= 64'h000000006FFF0000 &&
	     x__h406 < 64'h0000000000010000 ||
	     m_is_IO_addr_addr >= 64'h0000000062400000 &&
	     m_is_IO_addr_addr < 64'd1648365568 ||
	     NOT_m_is_IO_addr_addr_ULT_0x62300000_6___d47 &&
	     m_is_IO_addr_addr < 64'd1647316992 ||
	     m_is_IO_addr_addr >= 64'h0000000062310000 &&
	     m_is_IO_addr_addr < 64'd1647382528 ;
  assign NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d95 =
	     NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d70 ||
	     m_is_IO_addr_addr >= 64'h0000000062320000 &&
	     m_is_IO_addr_addr < 64'd1647448064 ||
	     m_is_IO_addr_addr >= 64'h0000000062360000 &&
	     m_is_IO_addr_addr < 64'd1647710208 ||
	     m_is_IO_addr_addr >= 64'h0000000062330000 &&
	     m_is_IO_addr_addr < 64'd1647513600 ||
	     m_is_IO_addr_addr >= 64'h0000000062370000 &&
	     m_is_IO_addr_addr < 64'd1647775744 ||
	     m_is_IO_addr_addr >= 64'h0000000020000000 &&
	     m_is_IO_addr_addr_ULT_0x30000000___d93 ;
  assign NOT_m_is_IO_addr_imem_not_dmem_2_AND_NOT_m_is__ETC___d99 =
	     !m_is_IO_addr_imem_not_dmem &&
	     (NOT_m_is_IO_addr_addr_ULT_0xC000000_3_4_AND_m__ETC___d95 ||
	      !m_is_IO_addr_addr_ULT_0x30000000___d93 &&
	      m_is_IO_addr_addr_ULT_1073741824___d16) ;
  assign m_is_IO_addr_addr_ULT_0x30000000___d93 =
	     m_is_IO_addr_addr < 64'h0000000030000000 ;
  assign m_is_IO_addr_addr_ULT_1073741824___d16 =
	     m_is_IO_addr_addr < 64'd1073741824 ;
  assign x__h181 = m_is_mem_addr_addr - 64'h00000000C0000000 ;
  assign x__h207 = m_is_IO_addr_addr - 64'h0000000070000000 ;
  assign x__h231 = m_is_IO_addr_addr - 64'h0000000080000000 ;
  assign x__h256 = m_is_IO_addr_addr - 64'h0000000040000000 ;
  assign x__h282 = m_is_IO_addr_addr - 64'h000000000C000000 ;
  assign x__h306 = m_is_IO_addr_addr - 64'h0000000010000000 ;
  assign x__h331 = m_is_IO_addr_addr - 64'h0000000062100000 ;
  assign x__h356 = m_is_IO_addr_addr - 64'h0000000062200000 ;
  assign x__h381 = m_is_IO_addr_addr - 64'h0000000062300000 ;
  assign x__h406 = m_is_IO_addr_addr - 64'h000000006FFF0000 ;
  assign x__h660 = m_is_near_mem_IO_addr_addr - 64'h0000000010000000 ;
endmodule  // mkSoC_Map