1018 lines
36 KiB
Verilog
1018 lines
36 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:18:54 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_write_enq O 1 const
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// read_deq O 370
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// RDY_read_deq O 1 const
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// RDY_setLSQAtCommitNotified O 1 const
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// RDY_setExecuted_deqLSQ O 1 const
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// RDY_setExecuted_doFinishAlu_0_set O 1 const
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// RDY_setExecuted_doFinishAlu_1_set O 1 const
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// RDY_setExecuted_doFinishFpuMulDiv_0_set O 1 const
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// RDY_setExecuted_doFinishMem O 1 const
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// getOrigPC O 129 reg
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// RDY_getOrigPC O 1 const
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// getOrigPredPC O 129
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// RDY_getOrigPredPC O 1 const
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// getOrig_Inst O 32 reg
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// RDY_getOrig_Inst O 1 const
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// dependsOn_wrongSpec O 1 reg
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// RDY_dependsOn_wrongSpec O 1 const
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// RDY_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// write_enq_x I 370
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// setExecuted_deqLSQ_cause I 14
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// setExecuted_deqLSQ_ld_killed I 3
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// setExecuted_doFinishAlu_0_set_csrData I 131
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// setExecuted_doFinishAlu_0_set_cause I 12
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// setExecuted_doFinishAlu_1_set_csrData I 131
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// setExecuted_doFinishAlu_1_set_cause I 12
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// setExecuted_doFinishFpuMulDiv_0_set_fflags I 5
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// setExecuted_doFinishMem_vaddr I 64
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// setExecuted_doFinishMem_access_at_commit I 1
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// setExecuted_doFinishMem_non_mmio_st_done I 1
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// dependsOn_wrongSpec_tag I 4
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// correctSpeculation_mask I 12
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// EN_write_enq I 1
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// EN_setLSQAtCommitNotified I 1
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// EN_setExecuted_deqLSQ I 1
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// EN_setExecuted_doFinishAlu_0_set I 1
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// EN_setExecuted_doFinishAlu_1_set I 1
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// EN_setExecuted_doFinishFpuMulDiv_0_set I 1
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// EN_setExecuted_doFinishMem I 1
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// EN_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// dependsOn_wrongSpec_tag -> dependsOn_wrongSpec
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkRobRowSynth(CLK,
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RST_N,
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write_enq_x,
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EN_write_enq,
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RDY_write_enq,
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read_deq,
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RDY_read_deq,
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EN_setLSQAtCommitNotified,
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RDY_setLSQAtCommitNotified,
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setExecuted_deqLSQ_cause,
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setExecuted_deqLSQ_ld_killed,
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EN_setExecuted_deqLSQ,
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RDY_setExecuted_deqLSQ,
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setExecuted_doFinishAlu_0_set_csrData,
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setExecuted_doFinishAlu_0_set_cause,
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EN_setExecuted_doFinishAlu_0_set,
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RDY_setExecuted_doFinishAlu_0_set,
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setExecuted_doFinishAlu_1_set_csrData,
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setExecuted_doFinishAlu_1_set_cause,
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EN_setExecuted_doFinishAlu_1_set,
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RDY_setExecuted_doFinishAlu_1_set,
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setExecuted_doFinishFpuMulDiv_0_set_fflags,
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EN_setExecuted_doFinishFpuMulDiv_0_set,
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RDY_setExecuted_doFinishFpuMulDiv_0_set,
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setExecuted_doFinishMem_vaddr,
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setExecuted_doFinishMem_access_at_commit,
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setExecuted_doFinishMem_non_mmio_st_done,
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EN_setExecuted_doFinishMem,
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RDY_setExecuted_doFinishMem,
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getOrigPC,
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RDY_getOrigPC,
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getOrigPredPC,
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RDY_getOrigPredPC,
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getOrig_Inst,
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RDY_getOrig_Inst,
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dependsOn_wrongSpec_tag,
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dependsOn_wrongSpec,
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RDY_dependsOn_wrongSpec,
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correctSpeculation_mask,
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EN_correctSpeculation,
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RDY_correctSpeculation);
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input CLK;
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input RST_N;
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// action method write_enq
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input [369 : 0] write_enq_x;
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input EN_write_enq;
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output RDY_write_enq;
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// value method read_deq
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output [369 : 0] read_deq;
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output RDY_read_deq;
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// action method setLSQAtCommitNotified
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input EN_setLSQAtCommitNotified;
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output RDY_setLSQAtCommitNotified;
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// action method setExecuted_deqLSQ
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input [13 : 0] setExecuted_deqLSQ_cause;
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input [2 : 0] setExecuted_deqLSQ_ld_killed;
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input EN_setExecuted_deqLSQ;
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output RDY_setExecuted_deqLSQ;
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// action method setExecuted_doFinishAlu_0_set
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input [130 : 0] setExecuted_doFinishAlu_0_set_csrData;
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input [11 : 0] setExecuted_doFinishAlu_0_set_cause;
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input EN_setExecuted_doFinishAlu_0_set;
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output RDY_setExecuted_doFinishAlu_0_set;
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// action method setExecuted_doFinishAlu_1_set
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input [130 : 0] setExecuted_doFinishAlu_1_set_csrData;
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input [11 : 0] setExecuted_doFinishAlu_1_set_cause;
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input EN_setExecuted_doFinishAlu_1_set;
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output RDY_setExecuted_doFinishAlu_1_set;
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// action method setExecuted_doFinishFpuMulDiv_0_set
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input [4 : 0] setExecuted_doFinishFpuMulDiv_0_set_fflags;
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input EN_setExecuted_doFinishFpuMulDiv_0_set;
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output RDY_setExecuted_doFinishFpuMulDiv_0_set;
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// action method setExecuted_doFinishMem
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input [63 : 0] setExecuted_doFinishMem_vaddr;
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input setExecuted_doFinishMem_access_at_commit;
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input setExecuted_doFinishMem_non_mmio_st_done;
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input EN_setExecuted_doFinishMem;
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output RDY_setExecuted_doFinishMem;
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// value method getOrigPC
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output [128 : 0] getOrigPC;
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output RDY_getOrigPC;
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// value method getOrigPredPC
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output [128 : 0] getOrigPredPC;
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output RDY_getOrigPredPC;
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// value method getOrig_Inst
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output [31 : 0] getOrig_Inst;
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output RDY_getOrig_Inst;
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// value method dependsOn_wrongSpec
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input [3 : 0] dependsOn_wrongSpec_tag;
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output dependsOn_wrongSpec;
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output RDY_dependsOn_wrongSpec;
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// action method correctSpeculation
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input [11 : 0] correctSpeculation_mask;
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input EN_correctSpeculation;
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output RDY_correctSpeculation;
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// signals for module outputs
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wire [369 : 0] read_deq;
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wire [128 : 0] getOrigPC, getOrigPredPC;
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wire [31 : 0] getOrig_Inst;
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wire RDY_correctSpeculation,
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RDY_dependsOn_wrongSpec,
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RDY_getOrigPC,
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RDY_getOrigPredPC,
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RDY_getOrig_Inst,
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RDY_read_deq,
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RDY_setExecuted_deqLSQ,
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RDY_setExecuted_doFinishAlu_0_set,
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RDY_setExecuted_doFinishAlu_1_set,
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RDY_setExecuted_doFinishFpuMulDiv_0_set,
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RDY_setExecuted_doFinishMem,
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RDY_setLSQAtCommitNotified,
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RDY_write_enq,
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dependsOn_wrongSpec;
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// inlined wires
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wire [130 : 0] m_ppc_vaddr_csrData_lat_0$wget,
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m_ppc_vaddr_csrData_lat_1$wget,
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m_ppc_vaddr_csrData_lat_2$wget,
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m_ppc_vaddr_csrData_lat_3$wget;
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wire [13 : 0] m_trap_lat_0$wget,
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m_trap_lat_1$wget,
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m_trap_lat_2$wget,
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m_trap_lat_3$wget;
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wire [2 : 0] m_ldKilled_lat_1$wget;
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wire m_rob_inst_state_lat_4$whas,
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m_trap_lat_0$whas,
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m_trap_lat_1$whas,
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m_trap_lat_2$whas;
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// register m_claimed_phy_reg
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reg m_claimed_phy_reg;
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wire m_claimed_phy_reg$D_IN, m_claimed_phy_reg$EN;
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// register m_csr
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reg [12 : 0] m_csr;
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wire [12 : 0] m_csr$D_IN;
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wire m_csr$EN;
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// register m_epochIncremented
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reg m_epochIncremented;
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wire m_epochIncremented$D_IN, m_epochIncremented$EN;
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// register m_fflags_rl
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reg [4 : 0] m_fflags_rl;
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wire [4 : 0] m_fflags_rl$D_IN;
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wire m_fflags_rl$EN;
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// register m_iType
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reg [4 : 0] m_iType;
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wire [4 : 0] m_iType$D_IN;
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wire m_iType$EN;
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// register m_ldKilled_rl
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reg [2 : 0] m_ldKilled_rl;
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wire [2 : 0] m_ldKilled_rl$D_IN;
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wire m_ldKilled_rl$EN;
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// register m_lsqAtCommitNotified_rl
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reg m_lsqAtCommitNotified_rl;
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wire m_lsqAtCommitNotified_rl$D_IN, m_lsqAtCommitNotified_rl$EN;
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// register m_lsqTag
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reg [5 : 0] m_lsqTag;
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wire [5 : 0] m_lsqTag$D_IN;
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wire m_lsqTag$EN;
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// register m_memAccessAtCommit_rl
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reg m_memAccessAtCommit_rl;
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wire m_memAccessAtCommit_rl$D_IN, m_memAccessAtCommit_rl$EN;
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// register m_nonMMIOStDone_rl
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reg m_nonMMIOStDone_rl;
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wire m_nonMMIOStDone_rl$D_IN, m_nonMMIOStDone_rl$EN;
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// register m_orig_inst
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reg [31 : 0] m_orig_inst;
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wire [31 : 0] m_orig_inst$D_IN;
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wire m_orig_inst$EN;
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// register m_pc
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reg [128 : 0] m_pc;
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wire [128 : 0] m_pc$D_IN;
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wire m_pc$EN;
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// register m_ppc_vaddr_csrData_rl
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reg [130 : 0] m_ppc_vaddr_csrData_rl;
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wire [130 : 0] m_ppc_vaddr_csrData_rl$D_IN;
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wire m_ppc_vaddr_csrData_rl$EN;
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// register m_rg_dst_reg
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reg [6 : 0] m_rg_dst_reg;
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wire [6 : 0] m_rg_dst_reg$D_IN;
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wire m_rg_dst_reg$EN;
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// register m_rob_inst_state_rl
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reg m_rob_inst_state_rl;
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wire m_rob_inst_state_rl$D_IN, m_rob_inst_state_rl$EN;
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// register m_scr
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reg [5 : 0] m_scr;
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wire [5 : 0] m_scr$D_IN;
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wire m_scr$EN;
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// register m_spec_bits_rl
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reg [11 : 0] m_spec_bits_rl;
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wire [11 : 0] m_spec_bits_rl$D_IN;
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wire m_spec_bits_rl$EN;
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// register m_trap_rl
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reg [13 : 0] m_trap_rl;
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wire [13 : 0] m_trap_rl$D_IN;
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wire m_trap_rl$EN;
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// register m_will_dirty_fpu_state
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reg m_will_dirty_fpu_state;
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wire m_will_dirty_fpu_state$D_IN, m_will_dirty_fpu_state$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_fflags_canon,
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CAN_FIRE_RL_m_ldKilled_canon,
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CAN_FIRE_RL_m_lsqAtCommitNotified_canon,
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CAN_FIRE_RL_m_memAccessAtCommit_canon,
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CAN_FIRE_RL_m_nonMMIOStDone_canon,
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CAN_FIRE_RL_m_ppc_vaddr_csrData_canon,
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CAN_FIRE_RL_m_rob_inst_state_canon,
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CAN_FIRE_RL_m_setPcWires,
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CAN_FIRE_RL_m_spec_bits_canon,
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CAN_FIRE_RL_m_trap_canon,
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CAN_FIRE_correctSpeculation,
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CAN_FIRE_setExecuted_deqLSQ,
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CAN_FIRE_setExecuted_doFinishAlu_0_set,
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CAN_FIRE_setExecuted_doFinishAlu_1_set,
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CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
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CAN_FIRE_setExecuted_doFinishMem,
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CAN_FIRE_setLSQAtCommitNotified,
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CAN_FIRE_write_enq,
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WILL_FIRE_RL_m_fflags_canon,
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WILL_FIRE_RL_m_ldKilled_canon,
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WILL_FIRE_RL_m_lsqAtCommitNotified_canon,
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WILL_FIRE_RL_m_memAccessAtCommit_canon,
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WILL_FIRE_RL_m_nonMMIOStDone_canon,
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WILL_FIRE_RL_m_ppc_vaddr_csrData_canon,
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WILL_FIRE_RL_m_rob_inst_state_canon,
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WILL_FIRE_RL_m_setPcWires,
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WILL_FIRE_RL_m_spec_bits_canon,
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WILL_FIRE_RL_m_trap_canon,
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WILL_FIRE_correctSpeculation,
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WILL_FIRE_setExecuted_deqLSQ,
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WILL_FIRE_setExecuted_doFinishAlu_0_set,
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WILL_FIRE_setExecuted_doFinishAlu_1_set,
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WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
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WILL_FIRE_setExecuted_doFinishMem,
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WILL_FIRE_setLSQAtCommitNotified,
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WILL_FIRE_write_enq;
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// remaining internal signals
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reg [1 : 0] CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
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CASE_m_trap_rl_BITS_12_TO_11_0_m_trap_rl_BITS__ETC__q2,
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CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q3,
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CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q5,
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CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q6,
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CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q7,
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CASE_write_enq_x_BITS_175_TO_174_0_write_enq_x_ETC__q4;
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wire [162 : 0] IF_m_ppc_vaddr_csrData_rl_01_BITS_130_TO_129_0_ETC___d302;
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wire [128 : 0] IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d114,
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IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d116;
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wire [63 : 0] IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d133,
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IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d135;
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wire [12 : 0] IF_IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_ETC___d82;
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wire [11 : 0] sb__h11692, upd__h6666;
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wire [10 : 0] IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d48,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d50;
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wire [4 : 0] IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d67,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d69;
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wire [3 : 0] IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d77,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d79;
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wire [1 : 0] IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d185;
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wire IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d175,
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IF_m_memAccessAtCommit_lat_1_whas__90_THEN_m_m_ETC___d196,
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IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d105,
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IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d124,
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IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d107,
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IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d126,
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IF_m_rob_inst_state_lat_3_whas__51_THEN_m_rob__ETC___d163,
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IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d16,
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IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d39,
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IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d58,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d18,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d41,
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IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d60;
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// action method write_enq
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assign RDY_write_enq = 1'd1 ;
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assign CAN_FIRE_write_enq = 1'd1 ;
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assign WILL_FIRE_write_enq = EN_write_enq ;
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// value method read_deq
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assign read_deq =
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{ m_pc,
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m_orig_inst,
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m_iType,
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m_rg_dst_reg,
|
|
m_scr,
|
|
m_csr,
|
|
m_claimed_phy_reg,
|
|
m_trap_rl[13],
|
|
CASE_m_trap_rl_BITS_12_TO_11_0_m_trap_rl_BITS__ETC__q2,
|
|
m_trap_rl[10:0],
|
|
IF_m_ppc_vaddr_csrData_rl_01_BITS_130_TO_129_0_ETC___d302 } ;
|
|
assign RDY_read_deq = 1'd1 ;
|
|
|
|
// action method setLSQAtCommitNotified
|
|
assign RDY_setLSQAtCommitNotified = 1'd1 ;
|
|
assign CAN_FIRE_setLSQAtCommitNotified = 1'd1 ;
|
|
assign WILL_FIRE_setLSQAtCommitNotified = EN_setLSQAtCommitNotified ;
|
|
|
|
// action method setExecuted_deqLSQ
|
|
assign RDY_setExecuted_deqLSQ = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_deqLSQ = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_deqLSQ = EN_setExecuted_deqLSQ ;
|
|
|
|
// action method setExecuted_doFinishAlu_0_set
|
|
assign RDY_setExecuted_doFinishAlu_0_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishAlu_0_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishAlu_0_set =
|
|
EN_setExecuted_doFinishAlu_0_set ;
|
|
|
|
// action method setExecuted_doFinishAlu_1_set
|
|
assign RDY_setExecuted_doFinishAlu_1_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishAlu_1_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishAlu_1_set =
|
|
EN_setExecuted_doFinishAlu_1_set ;
|
|
|
|
// action method setExecuted_doFinishFpuMulDiv_0_set
|
|
assign RDY_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set =
|
|
EN_setExecuted_doFinishFpuMulDiv_0_set ;
|
|
|
|
// action method setExecuted_doFinishMem
|
|
assign RDY_setExecuted_doFinishMem = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishMem = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishMem = EN_setExecuted_doFinishMem ;
|
|
|
|
// value method getOrigPC
|
|
assign getOrigPC = m_pc ;
|
|
assign RDY_getOrigPC = 1'd1 ;
|
|
|
|
// value method getOrigPredPC
|
|
assign getOrigPredPC =
|
|
(m_ppc_vaddr_csrData_rl[130:129] == 2'd0) ?
|
|
m_ppc_vaddr_csrData_rl[128:0] :
|
|
129'h000001FFFFC0180040000000000000000 ;
|
|
assign RDY_getOrigPredPC = 1'd1 ;
|
|
|
|
// value method getOrig_Inst
|
|
assign getOrig_Inst = m_orig_inst ;
|
|
assign RDY_getOrig_Inst = 1'd1 ;
|
|
|
|
// value method dependsOn_wrongSpec
|
|
assign dependsOn_wrongSpec = m_spec_bits_rl[dependsOn_wrongSpec_tag] ;
|
|
assign RDY_dependsOn_wrongSpec = 1'd1 ;
|
|
|
|
// action method correctSpeculation
|
|
assign RDY_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_correctSpeculation = EN_correctSpeculation ;
|
|
|
|
// rule RL_m_setPcWires
|
|
assign CAN_FIRE_RL_m_setPcWires = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_setPcWires = 1'd1 ;
|
|
|
|
// rule RL_m_trap_canon
|
|
assign CAN_FIRE_RL_m_trap_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_trap_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ppc_vaddr_csrData_canon
|
|
assign CAN_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
|
|
|
|
// rule RL_m_fflags_canon
|
|
assign CAN_FIRE_RL_m_fflags_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fflags_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rob_inst_state_canon
|
|
assign CAN_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldKilled_canon
|
|
assign CAN_FIRE_RL_m_ldKilled_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldKilled_canon = 1'd1 ;
|
|
|
|
// rule RL_m_memAccessAtCommit_canon
|
|
assign CAN_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
|
|
|
|
// rule RL_m_lsqAtCommitNotified_canon
|
|
assign CAN_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
|
|
|
|
// rule RL_m_nonMMIOStDone_canon
|
|
assign CAN_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign m_trap_lat_0$wget =
|
|
{ 3'd4, setExecuted_doFinishAlu_0_set_cause[10:0] } ;
|
|
assign m_trap_lat_0$whas =
|
|
EN_setExecuted_doFinishAlu_0_set &&
|
|
setExecuted_doFinishAlu_0_set_cause[11] ;
|
|
assign m_trap_lat_1$wget =
|
|
{ 3'd4, setExecuted_doFinishAlu_1_set_cause[10:0] } ;
|
|
assign m_trap_lat_1$whas =
|
|
EN_setExecuted_doFinishAlu_1_set &&
|
|
setExecuted_doFinishAlu_1_set_cause[11] ;
|
|
assign m_trap_lat_2$wget =
|
|
{ 1'd1,
|
|
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q3,
|
|
setExecuted_deqLSQ_cause[10:0] } ;
|
|
assign m_trap_lat_2$whas =
|
|
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[13] ;
|
|
assign m_trap_lat_3$wget =
|
|
{ write_enq_x[176],
|
|
CASE_write_enq_x_BITS_175_TO_174_0_write_enq_x_ETC__q4,
|
|
write_enq_x[173:163] } ;
|
|
assign m_ppc_vaddr_csrData_lat_0$wget =
|
|
{ CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q5,
|
|
setExecuted_doFinishAlu_0_set_csrData[128:0] } ;
|
|
assign m_ppc_vaddr_csrData_lat_1$wget =
|
|
{ CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q6,
|
|
setExecuted_doFinishAlu_1_set_csrData[128:0] } ;
|
|
assign m_ppc_vaddr_csrData_lat_2$wget =
|
|
{ 2'd1,
|
|
65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
setExecuted_doFinishMem_vaddr } ;
|
|
assign m_ppc_vaddr_csrData_lat_3$wget =
|
|
{ CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q7,
|
|
write_enq_x[160:32] } ;
|
|
assign m_rob_inst_state_lat_4$whas =
|
|
EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_non_mmio_st_done ;
|
|
assign m_ldKilled_lat_1$wget = { 1'd0, 2'bxx /* unspecified value */ } ;
|
|
|
|
// register m_claimed_phy_reg
|
|
assign m_claimed_phy_reg$D_IN = write_enq_x[177] ;
|
|
assign m_claimed_phy_reg$EN = EN_write_enq ;
|
|
|
|
// register m_csr
|
|
assign m_csr$D_IN = write_enq_x[190:178] ;
|
|
assign m_csr$EN = EN_write_enq ;
|
|
|
|
// register m_epochIncremented
|
|
assign m_epochIncremented$D_IN = write_enq_x[12] ;
|
|
assign m_epochIncremented$EN = EN_write_enq ;
|
|
|
|
// register m_fflags_rl
|
|
assign m_fflags_rl$D_IN =
|
|
EN_write_enq ?
|
|
write_enq_x[31:27] :
|
|
(EN_setExecuted_doFinishFpuMulDiv_0_set ?
|
|
setExecuted_doFinishFpuMulDiv_0_set_fflags :
|
|
m_fflags_rl) ;
|
|
assign m_fflags_rl$EN = 1'd1 ;
|
|
|
|
// register m_iType
|
|
assign m_iType$D_IN = write_enq_x[208:204] ;
|
|
assign m_iType$EN = EN_write_enq ;
|
|
|
|
// register m_ldKilled_rl
|
|
assign m_ldKilled_rl$D_IN =
|
|
{ IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d175,
|
|
IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d185 } ;
|
|
assign m_ldKilled_rl$EN = 1'd1 ;
|
|
|
|
// register m_lsqAtCommitNotified_rl
|
|
assign m_lsqAtCommitNotified_rl$D_IN =
|
|
!EN_write_enq &&
|
|
(EN_setLSQAtCommitNotified || m_lsqAtCommitNotified_rl) ;
|
|
assign m_lsqAtCommitNotified_rl$EN = 1'd1 ;
|
|
|
|
// register m_lsqTag
|
|
assign m_lsqTag$D_IN = write_enq_x[24:19] ;
|
|
assign m_lsqTag$EN = EN_write_enq ;
|
|
|
|
// register m_memAccessAtCommit_rl
|
|
assign m_memAccessAtCommit_rl$D_IN =
|
|
IF_m_memAccessAtCommit_lat_1_whas__90_THEN_m_m_ETC___d196 ;
|
|
assign m_memAccessAtCommit_rl$EN = 1'd1 ;
|
|
|
|
// register m_nonMMIOStDone_rl
|
|
assign m_nonMMIOStDone_rl$D_IN =
|
|
!EN_write_enq &&
|
|
(EN_setExecuted_doFinishMem ?
|
|
setExecuted_doFinishMem_non_mmio_st_done :
|
|
m_nonMMIOStDone_rl) ;
|
|
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
|
|
|
|
// register m_orig_inst
|
|
assign m_orig_inst$D_IN = write_enq_x[240:209] ;
|
|
assign m_orig_inst$EN = EN_write_enq ;
|
|
|
|
// register m_pc
|
|
assign m_pc$D_IN = write_enq_x[369:241] ;
|
|
assign m_pc$EN = EN_write_enq ;
|
|
|
|
// register m_ppc_vaddr_csrData_rl
|
|
assign m_ppc_vaddr_csrData_rl$D_IN =
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d107 ?
|
|
{ 2'd0,
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d116 } :
|
|
(IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d126 ?
|
|
{ 2'd1,
|
|
65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ,
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d135 } :
|
|
{ 2'd2,
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d116 }) ;
|
|
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
|
|
|
|
// register m_rg_dst_reg
|
|
assign m_rg_dst_reg$D_IN = write_enq_x[203:197] ;
|
|
assign m_rg_dst_reg$EN = EN_write_enq ;
|
|
|
|
// register m_rob_inst_state_rl
|
|
assign m_rob_inst_state_rl$D_IN =
|
|
EN_write_enq ?
|
|
write_enq_x[25] :
|
|
m_rob_inst_state_lat_4$whas ||
|
|
IF_m_rob_inst_state_lat_3_whas__51_THEN_m_rob__ETC___d163 ;
|
|
assign m_rob_inst_state_rl$EN = 1'd1 ;
|
|
|
|
// register m_scr
|
|
assign m_scr$D_IN = write_enq_x[196:191] ;
|
|
assign m_scr$EN = EN_write_enq ;
|
|
|
|
// register m_spec_bits_rl
|
|
assign m_spec_bits_rl$D_IN =
|
|
EN_correctSpeculation ? upd__h6666 : sb__h11692 ;
|
|
assign m_spec_bits_rl$EN = 1'd1 ;
|
|
|
|
// register m_trap_rl
|
|
assign m_trap_rl$D_IN =
|
|
{ IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d18,
|
|
IF_IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_ETC___d82 } ;
|
|
assign m_trap_rl$EN = 1'd1 ;
|
|
|
|
// register m_will_dirty_fpu_state
|
|
assign m_will_dirty_fpu_state$D_IN = write_enq_x[26] ;
|
|
assign m_will_dirty_fpu_state$EN = EN_write_enq ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_ETC___d82 =
|
|
IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d41 ?
|
|
{ 2'd0,
|
|
IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d50 } :
|
|
(IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d60 ?
|
|
{ 2'd1,
|
|
6'bxxxxxx /* unspecified value */ ,
|
|
IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d69 } :
|
|
{ 2'd2,
|
|
7'bxxxxxxx /* unspecified value */ ,
|
|
IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d79 }) ;
|
|
assign IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d175 =
|
|
EN_write_enq ?
|
|
m_ldKilled_lat_1$wget[2] :
|
|
(EN_setExecuted_deqLSQ ?
|
|
setExecuted_deqLSQ_ld_killed[2] :
|
|
m_ldKilled_rl[2]) ;
|
|
assign IF_m_ldKilled_lat_1_whas__66_THEN_m_ldKilled_l_ETC___d185 =
|
|
EN_write_enq ?
|
|
m_ldKilled_lat_1$wget[1:0] :
|
|
(EN_setExecuted_deqLSQ ?
|
|
setExecuted_deqLSQ_ld_killed[1:0] :
|
|
m_ldKilled_rl[1:0]) ;
|
|
assign IF_m_memAccessAtCommit_lat_1_whas__90_THEN_m_m_ETC___d196 =
|
|
EN_write_enq ?
|
|
write_enq_x[208:204] == 5'd19 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
setExecuted_doFinishMem_access_at_commit :
|
|
m_memAccessAtCommit_rl) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d105 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd0 :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd0 :
|
|
m_ppc_vaddr_csrData_rl[130:129] == 2'd0) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d114 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[128:0] :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[128:0] :
|
|
m_ppc_vaddr_csrData_rl[128:0]) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d124 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd1 :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd1 :
|
|
m_ppc_vaddr_csrData_rl[130:129] == 2'd1) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d133 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[63:0] :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[63:0] :
|
|
m_ppc_vaddr_csrData_rl[63:0]) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d107 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd0 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd0 :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d105) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d116 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[128:0] :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[128:0] :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d114) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d126 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd1 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd1 :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d124) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__5_THEN_m_pp_ETC___d135 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[63:0] :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[63:0] :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__3_THEN_m_pp_ETC___d133) ;
|
|
assign IF_m_ppc_vaddr_csrData_rl_01_BITS_130_TO_129_0_ETC___d302 =
|
|
{ CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
|
|
m_ppc_vaddr_csrData_rl[128:0],
|
|
m_fflags_rl,
|
|
m_will_dirty_fpu_state,
|
|
m_rob_inst_state_rl,
|
|
m_lsqTag,
|
|
m_ldKilled_rl,
|
|
m_memAccessAtCommit_rl,
|
|
m_lsqAtCommitNotified_rl,
|
|
m_nonMMIOStDone_rl,
|
|
m_epochIncremented,
|
|
m_spec_bits_rl } ;
|
|
assign IF_m_rob_inst_state_lat_3_whas__51_THEN_m_rob__ETC___d163 =
|
|
EN_setExecuted_deqLSQ ||
|
|
EN_setExecuted_doFinishFpuMulDiv_0_set ||
|
|
EN_setExecuted_doFinishAlu_1_set ||
|
|
EN_setExecuted_doFinishAlu_0_set ||
|
|
m_rob_inst_state_rl ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d16 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[13] :
|
|
(m_trap_lat_0$whas ? m_trap_lat_0$wget[13] : m_trap_rl[13]) ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d39 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[12:11] == 2'd0 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[12:11] == 2'd0 :
|
|
m_trap_rl[12:11] == 2'd0) ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d48 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[10:0] :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[10:0] :
|
|
m_trap_rl[10:0]) ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d58 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[12:11] == 2'd1 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[12:11] == 2'd1 :
|
|
m_trap_rl[12:11] == 2'd1) ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d67 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] :
|
|
(m_trap_lat_0$whas ? m_trap_lat_0$wget[4:0] : m_trap_rl[4:0]) ;
|
|
assign IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d77 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] :
|
|
(m_trap_lat_0$whas ? m_trap_lat_0$wget[3:0] : m_trap_rl[3:0]) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d18 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[13] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[13] :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d16) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d41 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[12:11] == 2'd0 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[12:11] == 2'd0 :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d39) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d50 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[10:0] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[10:0] :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d48) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d60 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[12:11] == 2'd1 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[12:11] == 2'd1 :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d58) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d69 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d67) ;
|
|
assign IF_m_trap_lat_3_whas_THEN_m_trap_lat_3_wget_BI_ETC___d79 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] :
|
|
IF_m_trap_lat_1_whas_THEN_m_trap_lat_1_wget_BI_ETC___d77) ;
|
|
assign sb__h11692 = EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
|
|
assign upd__h6666 = sb__h11692 & correctSpeculation_mask ;
|
|
always@(m_ppc_vaddr_csrData_rl)
|
|
begin
|
|
case (m_ppc_vaddr_csrData_rl[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1 =
|
|
m_ppc_vaddr_csrData_rl[130:129];
|
|
default: CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(m_trap_rl)
|
|
begin
|
|
case (m_trap_rl[12:11])
|
|
2'd0, 2'd1:
|
|
CASE_m_trap_rl_BITS_12_TO_11_0_m_trap_rl_BITS__ETC__q2 =
|
|
m_trap_rl[12:11];
|
|
default: CASE_m_trap_rl_BITS_12_TO_11_0_m_trap_rl_BITS__ETC__q2 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(setExecuted_deqLSQ_cause)
|
|
begin
|
|
case (setExecuted_deqLSQ_cause[12:11])
|
|
2'd0, 2'd1:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q3 =
|
|
setExecuted_deqLSQ_cause[12:11];
|
|
default: CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q3 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[175:174])
|
|
2'd0, 2'd1:
|
|
CASE_write_enq_x_BITS_175_TO_174_0_write_enq_x_ETC__q4 =
|
|
write_enq_x[175:174];
|
|
default: CASE_write_enq_x_BITS_175_TO_174_0_write_enq_x_ETC__q4 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_0_set_csrData)
|
|
begin
|
|
case (setExecuted_doFinishAlu_0_set_csrData[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q5 =
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129];
|
|
default: CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q5 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_1_set_csrData)
|
|
begin
|
|
case (setExecuted_doFinishAlu_1_set_csrData[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q6 =
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129];
|
|
default: CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q6 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[162:161])
|
|
2'd0, 2'd1:
|
|
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q7 =
|
|
write_enq_x[162:161];
|
|
default: CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q7 = 2'd2;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY
|
|
5'bxxxxx /* unspecified value */ ;
|
|
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY
|
|
3'bxxx /* unspecified value */ ;
|
|
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY
|
|
131'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'bx /* unspecified value */ ;
|
|
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY
|
|
12'bxxxxxxxxxxxx /* unspecified value */ ;
|
|
m_trap_rl <= `BSV_ASSIGNMENT_DELAY
|
|
14'bxxxxxxxxxxxxxx /* unspecified value */ ;
|
|
end
|
|
else
|
|
begin
|
|
if (m_fflags_rl$EN)
|
|
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY m_fflags_rl$D_IN;
|
|
if (m_ldKilled_rl$EN)
|
|
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY m_ldKilled_rl$D_IN;
|
|
if (m_lsqAtCommitNotified_rl$EN)
|
|
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_lsqAtCommitNotified_rl$D_IN;
|
|
if (m_memAccessAtCommit_rl$EN)
|
|
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_memAccessAtCommit_rl$D_IN;
|
|
if (m_nonMMIOStDone_rl$EN)
|
|
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY m_nonMMIOStDone_rl$D_IN;
|
|
if (m_ppc_vaddr_csrData_rl$EN)
|
|
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ppc_vaddr_csrData_rl$D_IN;
|
|
if (m_rob_inst_state_rl$EN)
|
|
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rob_inst_state_rl$D_IN;
|
|
if (m_spec_bits_rl$EN)
|
|
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_rl$D_IN;
|
|
if (m_trap_rl$EN) m_trap_rl <= `BSV_ASSIGNMENT_DELAY m_trap_rl$D_IN;
|
|
end
|
|
if (m_claimed_phy_reg$EN)
|
|
m_claimed_phy_reg <= `BSV_ASSIGNMENT_DELAY m_claimed_phy_reg$D_IN;
|
|
if (m_csr$EN) m_csr <= `BSV_ASSIGNMENT_DELAY m_csr$D_IN;
|
|
if (m_epochIncremented$EN)
|
|
m_epochIncremented <= `BSV_ASSIGNMENT_DELAY m_epochIncremented$D_IN;
|
|
if (m_iType$EN) m_iType <= `BSV_ASSIGNMENT_DELAY m_iType$D_IN;
|
|
if (m_lsqTag$EN) m_lsqTag <= `BSV_ASSIGNMENT_DELAY m_lsqTag$D_IN;
|
|
if (m_orig_inst$EN) m_orig_inst <= `BSV_ASSIGNMENT_DELAY m_orig_inst$D_IN;
|
|
if (m_pc$EN) m_pc <= `BSV_ASSIGNMENT_DELAY m_pc$D_IN;
|
|
if (m_rg_dst_reg$EN)
|
|
m_rg_dst_reg <= `BSV_ASSIGNMENT_DELAY m_rg_dst_reg$D_IN;
|
|
if (m_scr$EN) m_scr <= `BSV_ASSIGNMENT_DELAY m_scr$D_IN;
|
|
if (m_will_dirty_fpu_state$EN)
|
|
m_will_dirty_fpu_state <= `BSV_ASSIGNMENT_DELAY
|
|
m_will_dirty_fpu_state$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_claimed_phy_reg = 1'h0;
|
|
m_csr = 13'h0AAA;
|
|
m_epochIncremented = 1'h0;
|
|
m_fflags_rl = 5'h0A;
|
|
m_iType = 5'h0A;
|
|
m_ldKilled_rl = 3'h2;
|
|
m_lsqAtCommitNotified_rl = 1'h0;
|
|
m_lsqTag = 6'h2A;
|
|
m_memAccessAtCommit_rl = 1'h0;
|
|
m_nonMMIOStDone_rl = 1'h0;
|
|
m_orig_inst = 32'hAAAAAAAA;
|
|
m_pc = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_ppc_vaddr_csrData_rl = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rg_dst_reg = 7'h2A;
|
|
m_rob_inst_state_rl = 1'h0;
|
|
m_scr = 6'h2A;
|
|
m_spec_bits_rl = 12'hAAA;
|
|
m_trap_rl = 14'h2AAA;
|
|
m_will_dirty_fpu_state = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishAlu_0_set &&
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd0 &&
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd1 &&
|
|
!m_csr[12] &&
|
|
!m_scr[5])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishAlu_1_set &&
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd0 &&
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd1 &&
|
|
!m_csr[12] &&
|
|
!m_scr[5])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_access_at_commit &&
|
|
setExecuted_doFinishMem_non_mmio_st_done)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_non_mmio_st_done &&
|
|
m_iType != 5'd5)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[18])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[15])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[14])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[13])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkRobRowSynth
|
|
|