239 lines
8.2 KiB
Verilog
239 lines
8.2 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Thu Jul 16 18:15:02 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// capInspect O 64
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// capInspect_a I 163
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// capInspect_b I 163
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// capInspect_func I 4
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//
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// Combinational paths from inputs to outputs:
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// (capInspect_a, capInspect_b, capInspect_func) -> capInspect
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_capInspect(capInspect_a,
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capInspect_b,
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capInspect_func,
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capInspect);
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// value method capInspect
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input [162 : 0] capInspect_a;
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input [162 : 0] capInspect_b;
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input [3 : 0] capInspect_func;
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output [63 : 0] capInspect;
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// signals for module outputs
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reg [63 : 0] capInspect;
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// remaining internal signals
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reg [63 : 0] CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5;
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wire [65 : 0] addTop__h1361,
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addTop__h686,
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capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50,
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capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82,
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in__h2270,
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length__h2030,
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result__h1299,
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result__h1958,
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ret__h1365,
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ret__h690,
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x__h1358,
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x__h2025,
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x__h2288,
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x__h683,
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y__h2287;
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wire [63 : 0] addBase__h2072,
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addBase__h2423,
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bot__h2075,
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bot__h2426,
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x__h2234,
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x__h2236;
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wire [51 : 0] mask__h1362, mask__h687;
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wire [49 : 0] capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2,
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capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4,
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mask__h2073,
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mask__h2424;
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wire [30 : 0] x__h2326;
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wire [15 : 0] offset__h2222, x__h1451, x__h2035, x__h489, x__h623, x__h792;
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wire [1 : 0] capInspect_a_BITS_1_TO_0__q1, capInspect_b_BITS_1_TO_0__q3;
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wire capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63,
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capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95,
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capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39,
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x__h1510,
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x__h2164,
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x__h27,
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x__h851;
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// value method capInspect
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always@(capInspect_func or
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capInspect_a or
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bot__h2426 or
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x__h27 or
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x__h2025 or
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bot__h2075 or
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x__h2164 or
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x__h2234 or
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in__h2270 or
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x__h2326 or CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5)
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begin
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case (capInspect_func)
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4'd0: capInspect = { 63'd0, x__h27 };
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4'd2: capInspect = x__h2025[63:0];
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4'd3: capInspect = bot__h2075;
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4'd4: capInspect = { 63'd0, capInspect_a[162] };
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4'd5: capInspect = { 63'd0, x__h2164 };
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4'd6: capInspect = capInspect_a[159:96];
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4'd7: capInspect = x__h2234 | in__h2270[63:0];
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4'd8: capInspect = { 63'd0, capInspect_a[65] };
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4'd9: capInspect = { 33'd0, x__h2326 };
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4'd10:
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capInspect = CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5;
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default: capInspect =
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capInspect_a[162] ?
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capInspect_a[159:96] - bot__h2426 :
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64'd0;
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endcase
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end
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// remaining internal signals
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assign addBase__h2072 =
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{ {48{x__h489[15]}}, x__h489 } << capInspect_a[43:38] ;
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assign addBase__h2423 =
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{ {48{x__h623[15]}}, x__h623 } << capInspect_b[43:38] ;
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assign addTop__h1361 =
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{ {50{x__h1451[15]}}, x__h1451 } << capInspect_b[43:38] ;
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assign addTop__h686 =
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{ {50{x__h792[15]}}, x__h792 } << capInspect_a[43:38] ;
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assign bot__h2075 =
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{ capInspect_a[159:110] & mask__h2073, 14'd0 } + addBase__h2072 ;
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assign bot__h2426 =
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{ capInspect_b[159:110] & mask__h2424, 14'd0 } + addBase__h2423 ;
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assign capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2 =
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capInspect_a[159:110] +
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({ {48{capInspect_a_BITS_1_TO_0__q1[1]}},
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capInspect_a_BITS_1_TO_0__q1 } <<
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capInspect_a[43:38]) ;
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assign capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50 =
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{ capInspect_a[161:110] & mask__h687, 14'd0 } + addTop__h686 ;
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assign capInspect_a_BITS_1_TO_0__q1 = capInspect_a[1:0] ;
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assign capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63 =
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capInspect_a[43:38] < 6'd51 &&
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capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64:63] -
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{ 1'd0, x__h851 } >
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2'd1 ;
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assign capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4 =
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capInspect_b[159:110] +
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({ {48{capInspect_b_BITS_1_TO_0__q3[1]}},
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capInspect_b_BITS_1_TO_0__q3 } <<
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capInspect_b[43:38]) ;
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assign capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82 =
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{ capInspect_b[161:110] & mask__h1362, 14'd0 } + addTop__h1361 ;
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assign capInspect_b_BITS_1_TO_0__q3 = capInspect_b[1:0] ;
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assign capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95 =
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capInspect_b[43:38] < 6'd51 &&
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capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64:63] -
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{ 1'd0, x__h1510 } >
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2'd1 ;
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assign capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39 =
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capInspect_b[162] == capInspect_a[162] &&
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{ 12'd0,
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capInspect_a[81:78] & capInspect_b[81:78],
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3'd0,
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capInspect_a[77:66] & capInspect_b[77:66] } ==
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x__h2326 &&
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bot__h2075 >= bot__h2426 ;
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assign in__h2270 = capInspect_a[161:96] & y__h2287 ;
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assign length__h2030 = { 50'd0, x__h2035 } << capInspect_a[43:38] ;
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assign mask__h1362 = 52'hFFFFFFFFFFFFF << capInspect_b[43:38] ;
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assign mask__h2073 = 50'h3FFFFFFFFFFFF << capInspect_a[43:38] ;
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assign mask__h2424 = 50'h3FFFFFFFFFFFF << capInspect_b[43:38] ;
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assign mask__h687 = 52'hFFFFFFFFFFFFF << capInspect_a[43:38] ;
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assign offset__h2222 = { 2'd0, capInspect_a[95:82] } - x__h489 ;
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assign result__h1299 =
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{ 1'd0,
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~capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64],
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capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[63:0] } ;
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assign result__h1958 =
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{ 1'd0,
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~capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64],
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capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[63:0] } ;
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assign ret__h1365 =
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{ 1'd0,
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capInspect_b_BITS_161_TO_110_3_AND_45035996273_ETC___d82[64:0] } ;
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assign ret__h690 =
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{ 1'd0,
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capInspect_a_BITS_161_TO_110_1_AND_45035996273_ETC___d50[64:0] } ;
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assign x__h1358 =
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capInspect_b_BITS_43_TO_38_7_ULT_51_2_AND_NOT__ETC___d95 ?
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result__h1958 :
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ret__h1365 ;
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assign x__h1451 = { capInspect_b[3:2], capInspect_b[37:24] } ;
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assign x__h1510 =
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(capInspect_b[43:38] == 6'd50) ?
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capInspect_b[23] :
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capInspect_b_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q4[49] ;
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assign x__h2025 =
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(capInspect_a[43:38] < 6'd52) ?
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length__h2030 :
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66'h3FFFFFFFFFFFFFFFF ;
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assign x__h2035 = x__h792 - x__h489 ;
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assign x__h2164 = capInspect_a[62:45] != 18'd262143 ;
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assign x__h2234 = x__h2236 << capInspect_a[43:38] ;
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assign x__h2236 = { {48{offset__h2222[15]}}, offset__h2222 } ;
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assign x__h2288 = 66'h3FFFFFFFFFFFFFFFF << capInspect_a[43:38] ;
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assign x__h2326 =
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{ 12'd0, capInspect_a[81:78], 3'h0, capInspect_a[77:66] } ;
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assign x__h27 =
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capInspect_b_BIT_162_EQ_capInspect_a_BIT_162_A_ETC___d39 &&
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x__h683[64:0] <= x__h1358[64:0] ;
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assign x__h489 = { capInspect_a[1:0], capInspect_a[23:10] } ;
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assign x__h623 = { capInspect_b[1:0], capInspect_b[23:10] } ;
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assign x__h683 =
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capInspect_a_BITS_43_TO_38_6_ULT_51_0_AND_NOT__ETC___d63 ?
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result__h1299 :
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ret__h690 ;
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assign x__h792 = { capInspect_a[3:2], capInspect_a[37:24] } ;
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assign x__h851 =
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(capInspect_a[43:38] == 6'd50) ?
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capInspect_a[23] :
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capInspect_a_BITS_159_TO_110_PLUS_SEXT_capInsp_ETC__q2[49] ;
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assign y__h2287 = ~x__h2288 ;
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always@(capInspect_a)
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begin
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case (capInspect_a[62:45])
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18'd262140:
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CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 =
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64'hFFFFFFFFFFFFFFFC;
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18'd262141:
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CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 =
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64'hFFFFFFFFFFFFFFFD;
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18'd262142:
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CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 =
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64'hFFFFFFFFFFFFFFFE;
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18'd262143:
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CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 =
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64'hFFFFFFFFFFFFFFFF;
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default: CASE_capInspect_a_BITS_62_TO_45_262140_1844674_ETC__q5 =
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{ 46'd0, capInspect_a[62:45] };
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endcase
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end
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endmodule // module_capInspect
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