Nathaniel Filardo 6e4c378d4d CHERI ISAv8 CapDirty fault priority fix ...

Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

2020-11-06 19:15:47 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Bump BSV-RVFI-DII and refactor to support new parcel-based interface

2020-07-21 14:36:36 +01:00

CPU

Changes needed to build for FPGA.

2020-11-06 11:44:33 +00:00

Debug_Module

Cover interesting fetch and rename state for DEBUG_WEDGE configs

2020-07-10 15:59:40 +01:00

ISA

Replace enums-for-constants with structs wrapping a plain Bit#(n)

2020-07-15 03:16:24 +01:00

PLIC

Add CHERI+RVFI_DII grant codes and copyrights

2020-07-06 17:39:25 +01:00

RISCY_OOO

CHERI ISAv8 CapDirty fault priority fix

2020-11-06 19:15:47 +00:00