rsnikhil 75df204e31 Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values) ...

MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts.  However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.

2020-03-04 09:50:39 -05:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Fixed a Tandem-Verification issue (report MIP change due to interrupts).

2020-03-03 18:34:00 -05:00

CPU

Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values)

2020-03-04 09:50:39 -05:00

Debug_Module

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

ISA

Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow

2020-01-29 13:19:31 -05:00

PLIC

Initial load of files

2019-03-26 14:49:40 -04:00

RISCY_OOO

Fixed a Tandem-Verification issue (report MIP change due to interrupts).

2020-03-03 18:34:00 -05:00