rsnikhil 75df204e31 Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values) ...

MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts.  However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.

2020-03-04 09:50:39 -05:00

..

Core.bsv

Fixed Tandem Verif trace gen for CSRRx on WARL regs: report post-WARL-xformed write-data

2020-02-11 15:46:24 -05:00

CPU_Decode_C.bsv

Changes to support 'C' extension (compressed instructions). Details follow.

2019-04-09 13:50:16 -04:00

CsrFile.bsv

Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values)

2020-03-04 09:50:39 -05:00

LLC_AXI4_Adapter.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

MMIO_AXI4_Adapter.bsv

In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.

2020-02-28 14:07:45 -05:00

MMIOPlatform.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc_IFC.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00