Rishiyur S. Nikhil 8fc12c1dee Merge pull request #36 from h-chal/fix_rv64mi-p-access ...

fix: cache full virtual address for TLB micro-cache

(cherry picked from commit a79a4502c0e689058e6a2ffafd75b507c57ed3b9)

2025-10-31 18:07:27 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Revert "Use only 20 bits of address on the AXI lite port"

2024-11-12 17:44:11 +00:00

CPU

Revert "Give commit redirect priority over branch/execute redirect."

2025-07-03 11:46:43 +01:00

Debug_Module

Fix debug module reset state machine

2024-09-16 23:15:24 +01:00

ISA

Fix Toooba to use addresses instead of offsets (#32)

2025-02-05 11:06:07 +00:00

PLIC

Changes to build with a 512-bit main data bus (with all other busses

2022-11-11 17:52:32 +00:00

RISCY_OOO

Merge pull request #36 from h-chal/fix_rv64mi-p-access

2025-10-31 18:07:27 +00:00