Cheri-research/Toooba
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Toooba/src_Core/RISCY_OOO/procs/lib
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jon 1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. 
(Previously we ran into the limit of ports on the regFiles holding state
in the BTB.  This uses a vector of regFiles with a vector of interfaces,
which is logically the same but might produce multiple copies of state.)
2020-09-16 11:42:19 +01:00
..
Amo.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Bht.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
BrPred.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Btb.bsv
Enable larger than 2x superscalar by using explicit ports into the BTB.
2020-09-16 11:42:19 +01:00
Bypass.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
CacheUtils.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
CapChecks.bsvi
Report writes to PCC as illegal instruction, not ASR violation
2020-07-23 15:40:28 +01:00
ConcatReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
CSRs.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
Decode.bsv
Trap when writing PCC, rather than silently ignoring
2020-07-28 12:57:13 +01:00
DirPredictor.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
DTlb.bsv
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
Ehr.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
EpochManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Exceptions.bsvi
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
Exec.bsv
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
Fifos.bsv
FIFO optimisation both for build time (and possibly condition
2020-08-13 17:33:46 +01:00
FP_Utils.bsv
Add CHERI+RVFI_DII grant codes and copyrights
2020-07-06 17:39:25 +01:00
Fpu.bsv
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
FullAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalBrHistReg.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GlobalSpecUpdate.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
GSelectPred.bsv
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2020-07-06 17:39:25 +01:00
GSharePred.bsv
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2020-07-06 17:39:25 +01:00
HasSpecBits.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Interrupts.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
ITlb.bsv
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
L1CoCache.bsv
2-byte aligned instruction memory to simplify compressed instruction
2020-07-24 12:38:37 +01:00
L1LLConnect.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L2SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
L2Tlb.bsv
Add page table cap store checking
2020-07-21 16:02:37 +01:00
LatencyTimer.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
LLCache.bsv
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2020-07-06 17:39:25 +01:00
LLCDmaConnect.bsv
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2020-07-06 17:39:25 +01:00
LLCRqMshrSecureModel.bsv
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2020-07-06 17:39:25 +01:00
MemLoader.bsv
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2020-07-06 17:39:25 +01:00
MemLoaderIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
MemoryTypes.bsv
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2020-07-06 17:39:25 +01:00
MMIOAddrs.bsv
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2020-07-06 17:39:25 +01:00
MMIOCore.bsv
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2020-07-06 17:39:25 +01:00
MMIOInst.bsv
2-byte aligned instruction memory to simplify compressed instruction
2020-07-24 12:38:37 +01:00
MsgFifo.bsv
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2020-07-06 17:39:25 +01:00
MulDiv.bsv
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2020-07-06 17:39:25 +01:00
Opcodes.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
Performance.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
PhysRFile.bsv
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2020-07-06 17:39:25 +01:00
ProcTypes.bsv
2-byte aligned instruction memory to simplify compressed instruction
2020-07-24 12:38:37 +01:00
Ras.bsv
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2020-07-06 17:39:25 +01:00
RenameDebugIF.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
RenamingTable.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
ReorderBuffer.bsv
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
ReservationStationEhr.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
RVRoundModes.bsvi
Replace enums-for-constants with structs wrapping a plain Bit#(n)
2020-07-15 03:16:24 +01:00
SafeCounter.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
Scoreboard.bsv
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2020-07-06 17:39:25 +01:00
SetAssocTlb.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SpecFifo.bsv
Checkpoint FIFO scheduler work.
2020-07-08 12:39:13 +01:00
SpecPoisonFifo.bsv
Roll back changes to SpecPoisonFifo which were accidentally committed.
2020-07-09 15:19:39 +01:00
SpecTagManager.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
SplitLSQ.bsv
Add tag-clearing due to cap load perm and PTE bits
2020-07-22 15:54:49 +01:00
StoreBuffer.bsv
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2020-07-06 17:39:25 +01:00
TlbConnect.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
TlbTypes.bsv
Merge branch 'mem_perm_checks' into CHERI
2020-07-23 16:53:14 +01:00
TourPred.bsv
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2020-07-06 17:39:25 +01:00
TourPredSecure.bsv
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2020-07-06 17:39:25 +01:00
TranslationCache.bsv
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2020-07-06 17:39:25 +01:00
Types.bsv
2-byte aligned instruction memory to simplify compressed instruction
2020-07-24 12:38:37 +01:00
VerificationPacket.bsv
Initial load of files
2019-03-26 14:49:40 -04:00