8434df2dac
src_Core/CPU/CsrFile.bsv
Various fixes for WARL'd values of mstatus and sstatus, medeleg,
Added tval field in Trap_Updates returned by csrf.trap
src_Core/Core/Trace_Data2.bsv
Added fields for store_data and store_data_BE
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
Added treatment of store_data and store_data_BE
Fixed bug in next_pc for mkTrace_RET
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Fixed Trace_Data2 struct to TV for pc in case of xRET, and tval in case of trap
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
Added store_data and store_data_BE in calls to rob_setExecuted_doFinishMem
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Added store_data and store_data_BE in methods rob_setExecuted_doFinishMem
55 lines
1.9 KiB
Plaintext
55 lines
1.9 KiB
Plaintext
// Copyright (c) 2020 Bluespec, Inc. All Rights Reserved.
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package Trace_Data2;
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// ================================================================
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// Project imports
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// ----------------
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// From RISCY-OOO
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import Types :: *;
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import ProcTypes :: *;
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import ReorderBuffer :: *;
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// ================================================================
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// This struct has a subset of the fields of struct ToReorderBuffer in
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// Toooba/RISCY-OOO, to be encoded and emitted for Tandem
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// Verification.
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// In RISCY-OOO's CommitStage, when we dequeue (retire) an entry
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// (struct ToReorderBuffer), we simply copy out these fields and
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// enqueue this struct into a FIFO. All transformations/encoding for
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// TV are done on the dequeue side of the FIFO. Thus, this should not
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// add to the critical path or scheduling requirements of CommitStage.
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typedef struct {
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Bit #(64) serial_num; // TV message serial number
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Addr pc;
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Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
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IType iType;
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Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
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Data dst_data;
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Data store_data; // For mem instrs that store data
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ByteEn store_data_BE;
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Maybe #(CSR) csr;
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Maybe #(Trap) trap;
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Addr tval; // in case of trap
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PPCVAddrCSRData ppc_vaddr_csrData;
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Bit #(5) fflags;
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Bool will_dirty_fpu_state; // True means 2'b11 will be written to FS
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Data mstatus; // For Fpu ops, since [MX] bit may have changed
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// Trap updates
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Bit #(2) prv;
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Addr tvec;
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Data status;
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Data cause;
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Data epc;
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} Trace_Data2
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deriving (Bits, Eq, FShow);
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// ================================================================
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endpackage
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