rsnikhil 976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. ...

When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.

2020-03-08 21:29:30 -04:00

..

Core.bsv

Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)

2020-03-08 15:39:57 -04:00

CPU_Decode_C.bsv

Changes to support 'C' extension (compressed instructions). Details follow.

2019-04-09 13:50:16 -04:00

CsrFile.bsv

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00

LLC_AXI4_Adapter.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

MMIO_AXI4_Adapter.bsv

Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)

2020-03-08 15:39:57 -04:00

MMIOPlatform.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc_IFC.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00