rsnikhil 976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. ...

When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.

2020-03-08 21:29:30 -04:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00

CPU

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00

Debug_Module

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

ISA

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00

PLIC

Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)

2020-03-08 15:39:57 -04:00

RISCY_OOO

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00