Rishiyur S. Nikhil 9e72052437 Merge pull request #12 from jrtc27/step-fix ...

RenameStage.bsv: Fix single-step when only one instruction available

2020-04-07 09:14:55 -04:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)

2020-03-13 16:38:54 -04:00

CPU

Merge pull request #11 from CTSRD-CHERI/mac_build

2020-04-07 09:13:19 -04:00

Debug_Module

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

ISA

Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D

2020-03-09 14:47:20 -04:00

PLIC

Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)

2020-03-08 15:39:57 -04:00

RISCY_OOO

Merge pull request #12 from jrtc27/step-fix

2020-04-07 09:14:55 -04:00