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Merge pull request #11 from CTSRD-CHERI/mac_build

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Resolve some issues to build on mac.
This commit is contained in:
Rishiyur S. Nikhil
2020-04-07 09:13:19 -04:00
committed by GitHub
parent 6cfedfe1c8 b830f4bf41
commit 7accf2c1a0
38 changed files with 42 additions and 42 deletions
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2
builds/Resources/Include_verilator.mk
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@@ -34,7 +34,7 @@ SIM_EXE_FILE = exe_HW_sim
# --x-initial fast Optimize uninitialized value
# --noassert Disable all assertions
VERILATOR_FLAGS = --stats -LDFLAGS -static --x-assign fast --x-initial fast --noassert
VERILATOR_FLAGS = --stats --x-assign fast --x-initial fast --noassert
# VERILATOR_FLAGS = --stats -O3 -CFLAGS -O3 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
# Verilator flags: use the following to include code to generate VCDs

12
builds/Resources/Verilator_resources/verilator_config.vlt
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@@ -3,10 +3,10 @@
// Flags for verilator
`verilator_config
lint_off -msg WIDTH
lint_off -msg CASEINCOMPLETE
lint_off -msg STMTDLY
lint_off -msg INITIALDLY
lint_off -msg UNSIGNED
lint_off -msg CMPCONST
lint_off -rule WIDTH
lint_off -rule CASEINCOMPLETE
lint_off -rule STMTDLY
lint_off -rule INITIALDLY
lint_off -rule UNSIGNED
lint_off -rule CMPCONST
`verilog

2
src_Core/CPU/Core.bsv
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@@ -33,7 +33,7 @@ import Assert::*;
import Cntrs::*;
import ConfigReg::*;
import FIFO::*;
import Fifo::*;
import Fifos::*;
import Ehr::*;
import Connectable::*;

2
src_Core/CPU/CsrFile.bsv
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@@ -29,7 +29,7 @@ import DefaultValue::*;
import ConcatReg::*;
import ConfigReg::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import Vector::*;
import FIFO::*;
import GetPut::*;

2
src_Core/CPU/MMIOPlatform.bsv
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@@ -46,7 +46,7 @@ import GetPut_Aux :: *;
// ----------------
// From MIT RISCY-OOO
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import CCTypes::*;

2
src_Core/RISCY_OOO/coherence/src/CCPipe.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import Ehr::*;
import Fifo::*;
import Fifos::*;
import Vector::*;
import RWBramCore::*;
import FShow::*;

2
src_Core/RISCY_OOO/coherence/src/CrossBar.bsv
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@@ -28,7 +28,7 @@ import CacheUtils::*;
import CCTypes::*;
import Types::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import Ehr::*;
typedef struct {

2
src_Core/RISCY_OOO/coherence/src/IBank.bsv
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@@ -40,7 +40,7 @@ import CCPipe::*;
import L1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv
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@@ -31,7 +31,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
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@@ -41,7 +41,7 @@ import L1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import CrossBar::*;
import Performance::*;

2
src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv
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@@ -30,7 +30,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
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@@ -31,7 +31,7 @@ import CCPipe::*;
import LLPipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv
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@@ -30,7 +30,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import BRAMCore::*;
import Fifo::*;
import Fifos::*;
interface RWBramCore#(type addrT, type dataT);
method Action wrReq(addrT a, dataT d);

2
src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import Vector::*;
import Fifo::*;
import Fifos::*;
import CCTypes::*;
import RWBramCore::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
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@@ -39,7 +39,7 @@ import CCPipe::*;
import SelfInvIPipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
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@@ -26,7 +26,7 @@ import ConfigReg::*;
import Vector::*;
import FShow::*;
import Types::*;
import Fifo::*;
import Fifos::*;
import CCTypes::*;
import CCPipe::*;
import RWBramCore::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
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@@ -41,7 +41,7 @@ import SelfInvL1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import CrossBar::*;
import Performance::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
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@@ -25,7 +25,7 @@ import Assert::*;
import ConfigReg::*;
import Vector::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import CCTypes::*;
import CCPipe::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
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@@ -30,7 +30,7 @@ import LLCRqMshr::*;
import CCPipe::*;
import SelfInvLLPipe ::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -31,7 +31,7 @@ import ClientServer::*;
import Connectable::*;
import Decode::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import GetPut::*;
import MemoryTypes::*;
import Types::*;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -27,7 +27,7 @@ import BuildVector::*;
import GetPut::*;
import ClientServer::*;
import Cntrs::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import MemoryTypes::*;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -26,7 +26,7 @@
import Vector::*;
import GetPut::*;
import Cntrs::*;
import Fifo::*;
import Fifos::*;
import FIFO::*;
import Types::*;
import ProcTypes::*;

2
src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv
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@@ -29,7 +29,7 @@ import GetPut::*;
import ClientServer::*;
import Connectable::*;
import Vector::*;
import Fifo::*;
import Fifos::*;
import Ehr::*;
import FIFO::*;
import FIFOF::*;

2
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -31,7 +31,7 @@ import TlbTypes::*;
import Performance::*;
import FullAssocTlb::*;
import ConfigReg::*;
import Fifo::*;
import Fifos::*;
import Cntrs::*;
import SafeCounter::*;
import CacheUtils::*;

0
src_Core/RISCY_OOO/procs/lib/Fifo.bsv → src_Core/RISCY_OOO/procs/lib/Fifos.bsv
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2
src_Core/RISCY_OOO/procs/lib/ITlb.bsv
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@@ -31,7 +31,7 @@ import TlbTypes::*;
import Performance::*;
import FullAssocTlb::*;
import ConfigReg::*;
import Fifo::*;
import Fifos::*;
import Cntrs::*;
import SafeCounter::*;
import CacheUtils::*;

2
src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
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@@ -33,7 +33,7 @@ import CacheUtils::*;
import Types::*;
import ProcTypes::*;
import Performance::*;
import Fifo::*;
import Fifos::*;
import CCTypes::*;
import L1Pipe::*;
import L1CRqMshr::*;

2
src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
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@@ -33,7 +33,7 @@ import Performance::*;
import FullAssocTlb::*;
import ConfigReg::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import Cntrs::*;
import SafeCounter::*;
import CacheUtils::*;

2
src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv
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@@ -30,7 +30,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
import LLCRqMshr::*;

2
src_Core/RISCY_OOO/procs/lib/LLCache.bsv
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@@ -29,7 +29,7 @@ import Connectable::*;
import GetPut::*;
import Assert::*;
import CacheUtils::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import CCTypes::*;

2
src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv
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@@ -26,7 +26,7 @@ import ConfigReg::*;
import ProcTypes::*;
import MMIOAddrs::*;
import CacheUtils::*;
import Fifo::*;
import Fifos::*;
import Amo::*;
import MMIOInst::*;

2
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
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@@ -23,7 +23,7 @@
import Vector::*;
import ConfigReg::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import CCTypes::*;

2
src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
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@@ -29,7 +29,7 @@ import Connectable::*;
import FShow::*;
import FIFO::*;
import Vector::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import CCTypes::*;

2
src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv
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@@ -21,7 +21,7 @@
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
import Fifo::*;
import Fifos::*;
typedef union tagged {
reqT Req;

2
src_Core/RISCY_OOO/procs/lib/MulDiv.bsv
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@@ -25,7 +25,7 @@
import BuildVector::*;
import Types::*;
import ProcTypes::*;
import Fifo::*;
import Fifos::*;
import FIFO::*;
import XilinxIntMul::*;
import XilinxIntDiv::*;

2
src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv
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@@ -24,7 +24,7 @@
`include "ProcConfig.bsv"
import Vector::*;
import Fifo::*;
import Fifos::*;
import ProcTypes::*;
import CsrFile::*; // for mkReadOnlyReg
import Ehr::*;

2
src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv
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@@ -24,7 +24,7 @@
import Vector::*;
import Assert::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import ProcTypes::*;
import TlbTypes::*;