jon a77ecc59af Checkpoint work to propagate register numbers into the exception code. ...

There's another half of this left to do to propagate all the way into the CSR file.

2020-04-16 17:28:28 +01:00

..

BSV_Additional_Libs

Change tabs to 8 spaces, this time being careful to do this only in BSV files.

2020-03-23 14:44:39 +00:00

CHERI

Do the MTCC->PCC->MEPCC shuffle on trap.

2020-03-27 15:55:02 +00:00

Core

Port AXI4 changes from Flute

2020-03-27 16:45:26 +00:00

CPU

Move the register file to CapReg format, and pipe CapPipe around the pipeline.

2020-03-31 15:44:23 +01:00

Debug_Module

Change tabs to 8 spaces, this time being careful to do this only in BSV files.

2020-03-23 14:44:39 +00:00

ISA

Changes for CJALR to work in a basic case, as well as piping CHERI exceptions through to commit, though the register isn't piped and I've undone some useful work for that piping. Oh well.

2020-04-06 18:18:05 +01:00

PLIC

Port AXI4 changes from Flute

2020-03-27 16:45:26 +00:00

RISCY_OOO

Checkpoint work to propagate register numbers into the exception code.

2020-04-16 17:28:28 +01:00