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Do the MTCC->PCC->MEPCC shuffle on trap.

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This commit is contained in:
Jonathan Woodruff
2020-03-27 15:55:02 +00:00
parent 8d61c8db73
commit ded8dc72e7
2 changed files with 11 additions and 8 deletions
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16
src_Core/CHERI/ScrFile.bsv
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@@ -56,7 +56,7 @@ import SoC_Map::*;
// Information returned on traps and mret/sret/uret
typedef struct {
Addr new_pc;
Bit#(0) nothing_now;
} Scr_Trap_Updates
deriving (Bits, FShow);
@@ -90,7 +90,7 @@ interface ScrFile;
method CapReg warl_xform (SCR csr, CapReg x);
// Methods for handling traps
method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr faultAddr, Bit #(32) orig_inst);
method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
method ActionValue#(Scr_RET_Updates) sret;
method ActionValue#(Scr_RET_Updates) mret;
@@ -136,8 +136,8 @@ module mkScrFile (ScrFile);
let mkCsrEhr = mkConfigEhr;
// User level SCRs
Ehr#(SupSize, CapReg) pcc_reg <- mkCsrEhr(defaultValue);
Reg#(CapReg) ddc_reg <- mkCsrReg(defaultValue);
Ehr#(SupSize, CapReg) pcc_reg <- mkConfigEhr(defaultValue);
Reg#(CapReg) ddc_reg <- mkCsrReg(defaultValue);
// User level SCRs with accessSysRegs
Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue);
@@ -155,7 +155,7 @@ module mkScrFile (ScrFile);
Reg#(CapReg) mtcc_reg <- mkCsrReg(defaultValue);
Reg#(CapReg) mtdc_reg <- mkCsrReg(nullCap);
Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap);
Reg#(CapReg) mepcc_reg <- mkCsrReg(defaultValue);
Ehr#(2, CapReg) mepcc_reg <- mkConfigEhr(defaultValue);
// Function for getting a csr given an index
function Reg#(CapReg) get_scr(SCR scr);
@@ -177,7 +177,7 @@ module mkScrFile (ScrFile);
SCR_MTCC: mtcc_reg;
SCR_MTDC: mtdc_reg;
SCR_MScratchC: mScratchC_reg;
SCR_MEPCC: mepcc_reg;
SCR_MEPCC: mepcc_reg[1];
endcase);
endfunction
@@ -194,7 +194,9 @@ module mkScrFile (ScrFile);
interface pccWr = map(toPut,pcc_reg);
method ActionValue#(Scr_Trap_Updates) trap(Trap t, Addr pc, Addr addr, Bit #(32) orig_inst);
method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
mepcc_reg[0] <= cast(pc);
pcc_reg[0] <= mtcc_reg;
return ?;
endmethod

3
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -726,6 +726,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
: 1));
csrf.dcsr_cause_write (dcsr_cause);
csrf.dpc_write (trap.pc);
scaprfIfc.trap(trap.pc,?);
// Tell fetch stage to wait for redirect
// Note: rule doCommitTrap_flush may have done this already; redundant call is ok.
@@ -743,7 +744,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (! debugger_halt) begin
// trap handling & redirect
let trap_updates <- csrf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
let cap_trap_updates <- scaprf.trap(trap.trap, getAddr(trap.pc), trap.addr, trap.orig_inst);
let cap_trap_updates <- scaprf.trap(trap.pc, ?);
inIfc.redirectPc(trap_updates.new_pc
`ifdef RVFI_DII
, trap.x.diid + 1