rsnikhil 85e03fad21 Bugfix. Now passing rv64si-p-dirty ISA test. ...

Modified:
  src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
    In rule doPageWalk, if (!leafPte) ... else: added check for PPN alignment.
    (In mega-/giga-page PTEs, lower bits of PPN must be zero for alignment)

2019-04-11 14:30:53 -04:00

..

Resources

Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models

2019-04-04 13:10:45 -04:00

RV64ADFIMSU_Toooba_verilator

Bugfix. Now passing rv64si-p-dirty ISA test.

2019-04-11 14:30:53 -04:00