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Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models

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rsnikhil
2019-04-04 13:10:45 -04:00
parent 9f94c9176e
commit 47985fa93f
3 changed files with 5 additions and 2 deletions
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3
builds/RV64ADFIMSU_Toooba_verilator/Makefile
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@@ -39,6 +39,9 @@ TEST ?= rv64ui-p-add
#================================================================
# Parameter settings for MIT RISCY
BSC_COMPILATION_FLAGS += D BSIM \
include $(REPO)/builds/Resources/Include_RISCY_Config.mk
#================================================================

3
builds/Resources/Include_RISCY_Config.mk
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@@ -70,11 +70,10 @@ XILINX_INT_MUL_LATENCY = 2
BSC_COMPILATION_FLAGS += \
-D BSIM \
-D CORE_$(CORE_SIZE) \
-D NUM_CORES=$(CORE_NUM) \
-D CACHE_$(CACHE_SIZE) \
-D USE_XILINX_FPU \
-D USE_XILINX_FPU \
-D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
-D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
-D USE_BSV_BRAM_SYNC_FIFO \

1
src_SSITH_P3/Makefile
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@@ -37,6 +37,7 @@ BSC_COMPILATION_FLAGS += \
#================================================================
# Parameter settings for MIT RISCY
# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
include $(REPO)/builds/Resources/Include_RISCY_Config.mk