jon b4b7718aa2 Sort of support 2 cores for starting and halting.

2020-10-08 15:09:23 +01:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Bump BSV-RVFI-DII and refactor to support new parcel-based interface

2020-07-21 14:36:36 +01:00

CPU

Sort of support 2 cores for starting and halting.

2020-10-08 15:09:23 +01:00

Debug_Module

Cover interesting fetch and rename state for DEBUG_WEDGE configs

2020-07-10 15:59:40 +01:00

ISA

Replace enums-for-constants with structs wrapping a plain Bit#(n)

2020-07-15 03:16:24 +01:00

PLIC

Add CHERI+RVFI_DII grant codes and copyrights

2020-07-06 17:39:25 +01:00

RISCY_OOO

Change to allow 1-way superscalar to build without error.

2020-09-17 14:40:46 +01:00