jon b656f46859 Both enable tracing of floating-point register writes in RVFI-DII, and then properly not use them (since we're not expected to). ...

This is better than using nonsense as we were previously doing on floating point instructions.

2020-04-02 16:28:18 +01:00

..

BSV_Additional_Libs

Change tabs to 8 spaces, this time being careful to do this only in BSV files.

2020-03-23 14:44:39 +00:00

CHERI

Do the MTCC->PCC->MEPCC shuffle on trap.

2020-03-27 15:55:02 +00:00

Core

Port AXI4 changes from Flute

2020-03-27 16:45:26 +00:00

CPU

Move the register file to CapReg format, and pipe CapPipe around the pipeline.

2020-03-31 15:44:23 +01:00

Debug_Module

Change tabs to 8 spaces, this time being careful to do this only in BSV files.

2020-03-23 14:44:39 +00:00

ISA

An initial implementation of mccsr.

2020-03-27 17:47:02 +00:00

PLIC

Port AXI4 changes from Flute

2020-03-27 16:45:26 +00:00

RISCY_OOO

Both enable tracing of floating-point register writes in RVFI-DII, and then properly not use them (since we're not expected to).

2020-04-02 16:28:18 +01:00