Niraj N Sharma a0a4093088 Set verbosity to 0 in TV_Encode and Trace_Data2_to_Trace_Data ...

Updated src_SSITH_P3_sim SoC_Map

2020-01-30 13:39:54 -05:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Set verbosity to 0 in TV_Encode and Trace_Data2_to_Trace_Data

2020-01-30 13:39:54 -05:00

CPU

Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow

2020-01-29 13:19:31 -05:00

Debug_Module

Ensure that halt asserted after ndm reset is not ignored.

2019-04-09 14:08:36 -04:00

ISA

Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow

2020-01-29 13:19:31 -05:00

PLIC

Initial load of files

2019-03-26 14:49:40 -04:00

RISCY_OOO

Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow

2020-01-29 13:19:31 -05:00