265 lines
9.0 KiB
Plaintext
265 lines
9.0 KiB
Plaintext
//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package LLC_AXI4_Adapter;
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// ================================================================
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// BSV lib imports
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import ConfigReg :: *;
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import Assert :: *;
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import FIFOF :: *;
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import Vector :: *;
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// ----------------
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// BSV additional libs
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import GetPut_Aux :: *;
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import Cur_Cycle :: *;
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import Semi_FIFOF :: *;
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import CreditCounter :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From MIT RISCY-OOO
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import Types :: *;
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import CacheUtils :: *;
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import CCTypes :: *;
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// ----------------
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// From Bluespec Pipes
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import AXI4 :: *;
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import SourceSink :: *;
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import Fabric_Defs :: *;
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import SoC_Map :: *;
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// ================================================================
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interface LLC_AXI4_Adapter_IFC;
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method Action reset;
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// Fabric master interface for memory
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interface AXI4_Master #(Wd_MId, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) mem_master;
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endinterface
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// ================================================================
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module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
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(LLC_AXI4_Adapter_IFC)
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provisos(Bits#(idT, a__),
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Bits#(childT, b__),
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FShow#(ToMemMsg#(idT, childT)),
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FShow#(MemRsMsg#(idT, childT)),
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Add#(SizeOf#(Line), 0, TAdd#(512, 4))); // assert Line sz = 512 + 4 tags
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// Verbosity: 0: quiet; 1: LLC transactions; 2: loop detail
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Integer verbosity = 0;
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
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// ================================================================
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// Fabric request/response
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let masterPortShim <- mkAXI4ShimFF;
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// For discarding write-responses
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CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
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// ================================================================
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// Functions to interact with the fabric
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// Send a read-request into the fabric
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function Action fa_fabric_send_read_req (Fabric_Addr addr);
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action
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AXI4_Size size = 8;
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let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_default_mid,
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araddr: addr,
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arlen: 7, // burst len = arlen+1
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arsize: 8,
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arburst: INCR,
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arlock: fabric_default_lock,
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arcache: fabric_default_arcache,
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arprot: fabric_default_prot,
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arqos: fabric_default_qos,
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arregion: fabric_default_region,
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aruser: fabric_default_aruser};
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masterPortShim.slave.ar.put(mem_req_rd_addr);
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// Debugging
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if (cfg_verbosity > 1) begin
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$display (" ", fshow (mem_req_rd_addr));
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end
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endaction
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endfunction
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// ================================================================
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// Handle read requests and responses
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// Don't do reads while writes are outstanding.
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// Each 512b cache line takes 8 beats, each handling 64 bits
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Reg #(Bit #(3)) rg_rd_rsp_beat <- mkReg (0);
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FIFOF #(LdMemRq #(idT, childT)) f_pending_reads <- mkFIFOF;
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Reg #(CLine) rg_cline <- mkRegU;
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rule rl_handle_read_req (llc.toM.first matches tagged Ld .ld
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&&& (ctr_wr_rsps_pending.value == 0));
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if ((cfg_verbosity > 0)) begin
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$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory",
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cur_cycle);
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$display (" ", fshow (ld));
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end
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Addr line_addr = {ld.addr [63:6], 6'h0 }; // Addr of containing cache line
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fa_fabric_send_read_req (line_addr);
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f_pending_reads.enq (ld);
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llc.toM.deq;
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endrule
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rule rl_handle_read_rsps;
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let mem_rsp <- get(masterPortShim.slave.r);
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if (cfg_verbosity > 1) begin
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$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", cur_cycle, rg_rd_rsp_beat);
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$display (" ", fshow (mem_rsp));
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end
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if (mem_rsp.rresp != OKAY) begin
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// TODO: need to raise a non-maskable interrupt (NMI) here
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$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", cur_cycle);
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$display (" ", fshow (mem_rsp));
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$finish (1);
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end
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// Shift next 64 bits from fabric into the cache line being assembled
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let new_cline_tag = { mem_rsp.ruser, pack(rg_cline.tag) [3:1] };
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let new_cline_data = { mem_rsp.rdata, pack(rg_cline.data) [511:64] };
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let new_cline = CLine { tag: rg_rd_rsp_beat[0] == 0 ? unpack(new_cline_tag) : rg_cline.tag
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, data: unpack(new_cline_data) };
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if (mem_rsp.rlast) begin
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let ldreq <- pop (f_pending_reads);
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MemRsMsg #(idT, childT) resp = MemRsMsg {data: new_cline,
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child: ldreq.child,
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id: ldreq.id};
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llc.rsFromM.enq (resp);
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if (cfg_verbosity > 1)
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$display (" Response to LLC: ", fshow (resp));
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rg_rd_rsp_beat <= 0;
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rg_cline <= unpack(0);
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end else begin
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rg_rd_rsp_beat <= rg_rd_rsp_beat + 1;
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rg_cline <= new_cline;
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end
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endrule
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// ================================================================
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// Handle write requests and responses
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// Each 512b cache line takes 8 beats, each handling 64 bits
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Reg #(Bit #(3)) rg_wr_req_beat <- mkReg (0);
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rule rl_handle_write_req (llc.toM.first matches tagged Wb .wb);
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if ((cfg_verbosity > 0) && (rg_wr_req_beat == 0)) begin
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$display ("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", cur_cycle);
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$display (" ", fshow (wb));
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end
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// on first flit...
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// ================
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if (rg_wr_req_beat == 0) begin
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// send AXI4 AW flit
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masterPortShim.slave.aw.put (AXI4_AWFlit {
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awid: fabric_default_mid,
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awaddr: { wb.addr [63:6], 6'h0 },
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awlen: 7, // burst len = awlen+1
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awsize: 8,
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awburst: INCR,
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awlock: fabric_default_lock,
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awcache: fabric_default_awcache,
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awprot: fabric_default_prot,
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awqos: fabric_default_qos,
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awregion: fabric_default_region,
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awuser: 0});
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// Expect a fabric response
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ctr_wr_rsps_pending.incr;
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end
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// on last flit...
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// ===============
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if (rg_wr_req_beat == 7) begin
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llc.toM.deq;
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rg_wr_req_beat <= 0;
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end else // increment flit counter
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rg_wr_req_beat <= rg_wr_req_beat + 1;
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// on each flit ...
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// ================
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Vector #(8, Bit #(8)) line_strb = unpack(pack(wb.byteEn));
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Vector #(4, MemTaggedData) line_data = clineToMemTaggedDataVector(wb.data);
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// send AXI4 W flit
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masterPortShim.slave.w.put(AXI4_WFlit {
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wdata: line_data[rg_wr_req_beat[2:1]].data[rg_wr_req_beat[0]],
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wstrb: line_strb[rg_wr_req_beat],
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wlast: rg_wr_req_beat == 7,
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wuser: pack(line_data[rg_wr_req_beat[2:1]].tag)});
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endrule
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// ----------------
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// Discard write-responses from the fabric
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rule rl_discard_write_rsp;
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let wr_resp <- get(masterPortShim.slave.b);
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if (ctr_wr_rsps_pending.value == 0) begin
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$display ("%0d: ERROR: LLC_AXI4_Adapter.rl_discard_write_rsp: unexpected Wr response (ctr_wr_rsps_pending.value == 0)",
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cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1); // Assertion failure
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end
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ctr_wr_rsps_pending.decr;
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if (wr_resp.bresp != OKAY) begin
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// TODO: need to raise a non-maskable interrupt (NMI) here
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$display ("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1);
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end
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endrule
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// ================================================================
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// INTERFACE
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method Action reset;
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ctr_wr_rsps_pending.clear;
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endmethod
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// Fabric interface for memory
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interface mem_master = masterPortShim.master;
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endmodule
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// ================================================================
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endpackage
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