222 lines
6.3 KiB
Verilog
222 lines
6.3 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1
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// response_get O 69
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// RDY_response_get O 1
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 131
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkXilinxFpDivIP(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [130 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// register init_cnt
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reg [7 : 0] init_cnt;
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wire [7 : 0] init_cnt$D_IN;
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wire init_cnt$EN;
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// register init_init
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reg init_init;
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wire init_init$D_IN, init_init$EN;
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// register init_rg_ready
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reg init_rg_ready;
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wire init_rg_ready$D_IN, init_rg_ready$EN;
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// ports of submodule fpDiv
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wire [63 : 0] fpDiv$m_axis_result_tdata,
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fpDiv$s_axis_a_tdata,
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fpDiv$s_axis_b_tdata;
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wire [3 : 0] fpDiv$m_axis_result_tuser;
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wire fpDiv$m_axis_result_tready,
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fpDiv$m_axis_result_tvalid,
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fpDiv$s_axis_a_tready,
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fpDiv$s_axis_a_tvalid,
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fpDiv$s_axis_b_tready,
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fpDiv$s_axis_b_tvalid;
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// rule scheduling signals
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wire CAN_FIRE_RL_init_doInit,
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CAN_FIRE_RL_init_rg_rl_ready,
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CAN_FIRE_request_put,
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CAN_FIRE_response_get,
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WILL_FIRE_RL_init_doInit,
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WILL_FIRE_RL_init_rg_rl_ready,
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WILL_FIRE_request_put,
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WILL_FIRE_response_get;
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// action method request_put
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assign RDY_request_put =
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fpDiv$s_axis_a_tready && fpDiv$s_axis_b_tready && init_init &&
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init_rg_ready ;
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assign CAN_FIRE_request_put =
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fpDiv$s_axis_a_tready && fpDiv$s_axis_b_tready && init_init &&
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init_rg_ready ;
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assign WILL_FIRE_request_put = EN_request_put ;
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// actionvalue method response_get
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assign response_get =
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{ fpDiv$m_axis_result_tdata,
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fpDiv$m_axis_result_tuser[2],
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fpDiv$m_axis_result_tuser[3],
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fpDiv$m_axis_result_tuser[1:0],
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1'd0 } ;
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assign RDY_response_get =
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fpDiv$m_axis_result_tvalid && init_init && init_rg_ready ;
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assign CAN_FIRE_response_get =
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fpDiv$m_axis_result_tvalid && init_init && init_rg_ready ;
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assign WILL_FIRE_response_get = EN_response_get ;
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// submodule fpDiv
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fp_div fpDiv(.aclk(CLK),
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.s_axis_a_tdata(fpDiv$s_axis_a_tdata),
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.s_axis_b_tdata(fpDiv$s_axis_b_tdata),
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.s_axis_a_tvalid(fpDiv$s_axis_a_tvalid),
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.s_axis_b_tvalid(fpDiv$s_axis_b_tvalid),
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.m_axis_result_tready(fpDiv$m_axis_result_tready),
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.s_axis_a_tready(fpDiv$s_axis_a_tready),
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.s_axis_b_tready(fpDiv$s_axis_b_tready),
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.m_axis_result_tvalid(fpDiv$m_axis_result_tvalid),
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.m_axis_result_tdata(fpDiv$m_axis_result_tdata),
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.m_axis_result_tuser(fpDiv$m_axis_result_tuser));
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// rule RL_init_doInit
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assign CAN_FIRE_RL_init_doInit = !init_init ;
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assign WILL_FIRE_RL_init_doInit = CAN_FIRE_RL_init_doInit ;
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// rule RL_init_rg_rl_ready
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assign CAN_FIRE_RL_init_rg_rl_ready = 1'd1 ;
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assign WILL_FIRE_RL_init_rg_rl_ready = 1'd1 ;
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// register init_cnt
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assign init_cnt$D_IN = init_cnt + 8'd1 ;
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assign init_cnt$EN = CAN_FIRE_RL_init_doInit ;
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// register init_init
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assign init_init$D_IN = 1'd1 ;
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assign init_init$EN = WILL_FIRE_RL_init_doInit && init_cnt == 8'd255 ;
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// register init_rg_ready
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assign init_rg_ready$D_IN = 1'd1 ;
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assign init_rg_ready$EN = 1'd1 ;
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// submodule fpDiv
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assign fpDiv$s_axis_a_tdata = request_put[130:67] ;
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assign fpDiv$s_axis_b_tdata = request_put[66:3] ;
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assign fpDiv$s_axis_a_tvalid = EN_request_put ;
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assign fpDiv$s_axis_b_tvalid = EN_request_put ;
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assign fpDiv$m_axis_result_tready = EN_response_get ;
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// handling of inlined registers
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always@(posedge CLK)
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begin
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if (RST_N == `BSV_RESET_VALUE)
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begin
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init_cnt <= `BSV_ASSIGNMENT_DELAY 8'd0;
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init_init <= `BSV_ASSIGNMENT_DELAY 1'd0;
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init_rg_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
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end
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else
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begin
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if (init_cnt$EN) init_cnt <= `BSV_ASSIGNMENT_DELAY init_cnt$D_IN;
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if (init_init$EN) init_init <= `BSV_ASSIGNMENT_DELAY init_init$D_IN;
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if (init_rg_ready$EN)
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init_rg_ready <= `BSV_ASSIGNMENT_DELAY init_rg_ready$D_IN;
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end
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end
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// synopsys translate_off
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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initial
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begin
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init_cnt = 8'hAA;
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init_init = 1'h0;
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init_rg_ready = 1'h0;
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end
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`endif // BSV_NO_INITIAL_BLOCKS
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// synopsys translate_on
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// handling of system tasks
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// synopsys translate_off
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always@(negedge CLK)
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begin
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#0;
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] != 3'd0)
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$fwrite(32'h80000002,
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"[Xlinx DIV] WARNING: unsupported rounding mode ");
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] == 3'd1)
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$fwrite(32'h80000002, "<Round Mode: Nearest Away From Zero>");
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] == 3'd2)
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$fwrite(32'h80000002, "<Round Mode: +Infinity>");
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] == 3'd3)
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$fwrite(32'h80000002, "<Round Mode: -Infinity>");
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] != 3'd0 &&
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request_put[2:0] != 3'd1 &&
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request_put[2:0] != 3'd2 &&
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request_put[2:0] != 3'd3)
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$fwrite(32'h80000002, "<Round Mode: Zero>");
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_request_put && request_put[2:0] != 3'd0)
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$fwrite(32'h80000002, "\n");
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end
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// synopsys translate_on
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endmodule // mkXilinxFpDivIP
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