68d3bd484e
When DEBUG_WEDGE is defined, expose the last committed and next in the reorder buffer PC and corresponding instruction via DMI registers, since even when the core is wedged and we can't read GPRs etc we can still interact with the debug module itself. Hopefully this proves useful for debugging wedges.
139 lines
4.4 KiB
Makefile
139 lines
4.4 KiB
Makefile
### -*-Makefile-*-
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# ================================================================
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.PHONY: help
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help:
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@echo ' make compile Recompile Core (CPU, caches) into Verilog_RTL and copies into xilinx_ip/hdl'
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@echo ' NOTE: needs Bluespec bsc compiler'
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@echo ''
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@echo ' make clean Remove intermediate build-files'
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@echo ' make full_clean Restore this directory to pristine state'
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.PHONY: compile
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compile: compile_sim compile_synth
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# ================================================================
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REPO ?= ..
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ARCH ?= RV64ACDFIMSUxCHERI
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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BSC_COMPILATION_FLAGS += \
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-D RV64 \
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-D ISA_PRIV_M -D ISA_PRIV_S -D ISA_PRIV_U \
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-D SV39 \
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-D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \
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-D CheriBusBytes=8 \
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-D CheriMasterIDWidth=1 \
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-D CheriTransactionIDWidth=5 \
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-D SHIFT_BARREL \
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-D MULT_SERIAL \
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-D Near_Mem_Caches \
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-D FABRIC64 \
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-D CAP128 \
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-D MEM64 \
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-D RISCV \
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-D INCLUDE_GDB_CONTROL \
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-D BRVF_TRACE \
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-D XILINX_BSCAN -D JTAG_TAP
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# Enable to expose last and next instruction info as DMI registers
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#BSC_COMPILATION_FLAGS += -D DEBUG_WEDGE
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# Synth only BSC_COMPILATION_FLAGS
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SYNTH_BSC_OPTIONS = -D XILINX_XCVU9P
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# Sim only BSC_COMPILATION_FLAGS
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SIM_BSC_OPTIONS = -D BSIM
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# Only used if we don't have INCLUDE_GDB_CONTROL
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# -D EXTERNAL_DEBUG_MODULE
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include $(REPO)/builds/Resources/Include_RISCY_Config.mk
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# ================================================================
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# Path to RISCY-OOO sources
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RISCY_HOME ?= ../src_Core/RISCY_OOO
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RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib
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CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv
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CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib
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# ALL_RISCY_DIRS = $(RISCY_DIRS)
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ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
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# ================================================================
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# Search path for bsc for .bsv files
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CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(REPO)/src_Core/PLIC:$(REPO)/src_Core/Debug_Module:$(REPO)/src_Core/BSV_Additional_Libs
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BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics
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TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore
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BSC_PATH = -p $(ALL_RISCY_DIRS):$(CORE_DIRS):src_BSV:$(BLUESTUFF_DIRS):$(TAGCONTROLLER_DIRS):+:%/Libraries/TLM3:%/Libraries/Axi:%/Libraries/Axi4
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# ----------------
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# Top-level file and module
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TOPFILE = src_BSV/P3_Core.bsv
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TOPMODULE = mkP3_Core
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# ================================================================
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# More bsc compilation flags
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BSC_COMPILATION_FLAGS += \
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-keep-fires -aggressive-conditions \
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-no-warn-action-shadowing \
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-suppress-warnings G0020 \
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+RTS -K128M -RTS -show-range-conflict \
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-steps-max-intervals 10000000
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# ================================================================
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# Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)
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BUILD_DIRS_SYNTH = -bdir build_dir_synth -info-dir build_dir_synth
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BUILD_DIRS_SIM = -bdir build_dir_sim -info-dir build_dir_sim
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build_dir_synth:
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mkdir -p $@
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build_dir_sim:
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mkdir -p $@
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Verilog_RTL:
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mkdir -p $@
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Verilog_RTL_sim:
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mkdir -p $@
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.PHONY: compile_synth
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compile_synth: build_dir_synth Verilog_RTL
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@echo "INFO: Generating RTL into Verilog_RTL for synthesis ..."
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bsc -u -elab -verilog -vdir Verilog_RTL $(BUILD_DIRS_SYNTH) $(BSC_COMPILATION_FLAGS) $(SYNTH_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)
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@echo "INFO: Generated Synth RTL into Verilog_RTL"
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cp Verilog_RTL/* xilinx_ip/hdl/
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@echo "INFO: Copied RTL from Verilog_RTL/ to xilinx_ip/hdl/"
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.PHONY: compile_sim
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compile_sim: build_dir_sim Verilog_RTL_sim
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@echo "INFO: Generating RTL into Verilog_RTL_sim for simulation ..."
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bsc -u -elab -verilog -vdir Verilog_RTL_sim $(BUILD_DIRS_SIM) $(BSC_COMPILATION_FLAGS) $(SIM_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)
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# ================================================================
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.PHONY: clean
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clean:
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rm -r -f *~ Makefile_* build_dir_sim build_dir_synth
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.PHONY: full_clean
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full_clean: clean
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rm -r -f *.log Verilog_RTL Verilog_RTL_sim
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# ================================================================
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