5d69e3b178
Modified:
src_Core/CPU/CsrFile.bsv
Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
for InstAccessFault and InstPageFault
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
for InstAccessFault and InstPageFault
LICENSE
README.md
Clarified licensing of MIT code and Bluespec code
Tests/Run_regression.py
Emptied out 'exclude_list'
builds/RV64ADFIMSU_Toooba_verilator/Makefile
Added 'C' to Makefile
68 lines
2.3 KiB
Markdown
68 lines
2.3 KiB
Markdown
# Open-source RISC-V CPUs from Bluespec, Inc.
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***** UNDER CONSTRUCTION *****
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***** PLEASE COME BACK LATER (EARLY APRIL 2019) *****
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This is one of a family of free, open-source RISC-V CPUs created by Bluespec, Inc.
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- [Piccolo](https://github.com/bluespec/Piccolo): 3-stage, in-order pipeline
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Piccolo is intended for low-end applications (Embedded Systems, IoT, microcontrollers, etc.).
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- [Flute](https://github.com/bluespec/Flute): 5-stage, in-order pipeline
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Flute is intended for low-end to medium applications that require
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64-bit operation, an MMU (Virtual Memory) and more performance than
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Piccolo-class processors.
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- [Tooba](https://github.com/bluespec/Tooba): superscalar, out-of-order
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pipeline, slight variation on MIT's RISCY-OOO [In progress!]
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----------------------------------------------------------------
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### Note re. distribution of MIT RISCY-OOO sources.
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The directory `src_Core/RISCY_OOO` contains sources copied from MIT's
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`riscy-OOO` repository. See `LICENSE_RISCY-OOO` for MIT's license.
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[Note: MIT's repository is on an MIT git server, which can only be
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accessed with credentials; hence the local copy in of these files.]
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Bluespec's modifications to files in src_Core/RISCY_OOO are relatively
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small and mostly additive:
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- To add the RISC-V 'C' extension (compressed instructions)
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- To add support for Bluespec's Tandem Verification
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- To add support for Bluespec's Debug Module.
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----------------------------------------------------------------
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### Building and running Tooba
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You will need:
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- A Bluespec tools installation (so you can run 'bsc', the Bluespec
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compiler for BSV). We recommend version 2018.10.beta1 or later.
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- A Verilator installation. We recommend version 3.922 or later.
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Then:
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$ cd builds/RV64ADFIMSU_Tuba_verilator
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$ make all
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This will compile BSV sources using the 'bsc' compiler into Verilog in
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the directory `Verilog_RTL`, then compile and link into a verilator
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executable `exe_HW_sim`.
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Then:
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$ make test (1)
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$ make TEST=<isa_test_name> test (2)
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$ make isa_tests (3)
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(1) Will run a single ISA test, `rv64ui-p-add`.
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(2) Will do the same, but with the ISA test whose name you supply.
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(3) Will run ISA tests for RV64G.
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----------------------------------------------------------------
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