113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
109 lines
2.8 KiB
Plaintext
109 lines
2.8 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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package Proc_IFC;
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// ================================================================
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// BSV library imports
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import GetPut :: *;
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import ClientServer :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import DM_CPU_Req_Rsp :: *;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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import TV_Info :: *;
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`endif
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// ================================================================
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// CPU interface
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// Note: this Proc_IFC is similar, but not identical to CPU_IFC for Piccolo and Flute
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// Specifically, it removes interfaces for software and timer,
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// because the RISCY-OOO mkProc contains those elements.
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interface Proc_IFC;
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// Reset
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interface Server #(Token, Token) hart0_server_reset;
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// ----------------
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// Start the cores running
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method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
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// ----------------
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// SoC fabric connections
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// Fabric master interface for memory (from LLC)
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master0;
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// Fabric master interface for IO (from MMIOPlatform)
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master1;
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// ----------------
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// External interrupts
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(* always_ready, always_enabled *)
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method Action m_external_interrupt_req (Bool set_not_clear);
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(* always_ready, always_enabled *)
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method Action s_external_interrupt_req (Bool set_not_clear);
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// ----------------
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// External interrupt [14] to go into Debug Mode
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(* always_ready, always_enabled *)
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method Action debug_external_interrupt_req (Bool set_not_clear);
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// ----------------
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// Non-maskable interrupt
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(* always_ready, always_enabled *)
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method Action non_maskable_interrupt_req (Bool set_not_clear);
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// ----------------
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// Set core's verbosity
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method Action set_verbosity (Bit #(4) verbosity);
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// ----------------
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// Optional interface to Tandem Verifier
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`ifdef INCLUDE_TANDEM_VERIF
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interface Get #(Trace_Data) trace_data_out;
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`endif
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// ----------------
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// Optional interface to Debug Module
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`ifdef INCLUDE_GDB_CONTROL
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// run-control, other
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interface Server #(Bool, Bool) hart0_server_run_halt;
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interface Put #(Bit #(4)) hart0_put_other_req;
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// GPR access
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interface Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) hart0_gpr_mem_server;
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`ifdef ISA_F
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// FPR access
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interface Server #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN)) hart0_fpr_mem_server;
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`endif
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// CSR access
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interface Server #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_server;
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`endif
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endinterface
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// ================================================================
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endpackage
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