Modified:
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
Bug fixes in 'getTrap' function:
- Trap if Fpu regs are accessed but mstatus_fs is "Off" (2'b00)
- Trap if r/w or privilege denies access to CSR in CSRRW/C/S instruction
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
Bug fix: add support for 'u' bit in function 'getExtensionBits'